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Volumn , Issue , 2004, Pages 44-47

Multifunction subthreshold gate used for a low power full adder

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ELECTRIC INVERTERS; ELECTRIC POTENTIAL; ENERGY UTILIZATION; GATES (TRANSISTOR); MOSFET DEVICES; NEURAL NETWORKS; POWER ELECTRONICS;

EID: 21244447427     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (14)
  • 3
    • 21244494171 scopus 로고    scopus 로고
    • Norwegian patent application number 20035537, filed December 11
    • S. Aunet; Kretselement Norwegian patent application number 20035537, filed December 11,2003.
    • (2003) Kretselement
    • Aunet, S.1
  • 5
    • 0035242870 scopus 로고    scopus 로고
    • Robust subthreshold logic for ultra-low power operation
    • Feb.
    • H. Soeleman, K. Roy, Bipul C. Paul; Robust Subthreshold Logic for Ultra-Low Power Operation IEEE Trans. on VLSI, V 9, pp 90-99, Feb. 2001.
    • (2001) IEEE Trans. on VLSI , vol.9 , pp. 90-99
    • Soeleman, H.1    Roy, K.2    Paul, B.C.3
  • 6
    • 21244496937 scopus 로고    scopus 로고
    • Self Adjusting Threshold-Voltage Scheme (SATS) for low-voltage high speed operation
    • Las Cruces, NM, USA, August
    • T. Kobayashi, T. Sakurai; Self Adjusting Threshold-Voltage Scheme (SATS) for Low-Voltage High Speed Operation Proceedings of the 42nd Midwest Symposium on Circuits and Systems, Vol. 1, pp 6-9, Las Cruces, NM, USA, August 1999.
    • (1999) Proceedings of the 42nd Midwest Symposium on Circuits and Systems , vol.1 , pp. 6-9
    • Kobayashi, T.1    Sakurai, T.2
  • 8
    • 0141485506 scopus 로고    scopus 로고
    • VLSI implementations of threshold logic - A comprehensive survey
    • Sept.
    • V. Beiu, J. M. Quintana, and M. J. Avedillo; VLSI Implementations of Threshold Logic - a Comprehensive Survey, IEEE Trans. on Neural Networks,V 14, pp. 1217-1243, Sept. 2003.
    • (2003) IEEE Trans. on Neural Networks , vol.14 , pp. 1217-1243
    • Beiu, V.1    Quintana, J.M.2    Avedillo, M.J.3
  • 13
    • 0242443318 scopus 로고    scopus 로고
    • Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS
    • Sept.
    • S. Aunet, Y. Berg, T. Sæther; Real-time Reconfigurable Linear Threshold Elements Implemented in Floating-Gate CMOS, IEEE Trans. on Neural Networks,V 14, pp. 1244-1256, Sept. 2003.
    • (2003) IEEE Trans. on Neural Networks , vol.14 , pp. 1244-1256
    • Aunet, S.1    Berg, Y.2    Sæther, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.