Relaxation processes in strained Si layers on silicon-germanium- on-insulator substrates

Applied Physics Letters

Volumn 86, Issue 22, 2005, Pages 1-3

  Hirashita, Norio ^a   Sugiyama, Naoharu ^a   Toyoda, Eiji ^b   Takagi, Shin Ichi ^c  

^a TOSHIBA CORPORATION   (Japan)

^b Nissei Bldg   (Japan)

^c NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DISLOCATIONS (CRYSTALS); ELECTRIC FURNACE PROCESS; GERMANIUM; MOSFET DEVICES; RELAXATION PROCESSES; SILICON ON INSULATOR TECHNOLOGY; THERMAL EFFECTS;

CLASSIC PYROELECTRIC EFFECTS (APE); FREE ENERGY DENSITY; SPATIAL DEPENDENCE; TAYLOR SERIES;

SILICON COMPOUNDS;

EID: 20844459766     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1944208     Document Type: Article

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