Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 6, 2005, Pages 1303-1308

  Nonis, Roberto ^a   Da Dalt, Nicola ^b   Palestri, Pierpaolo ^a   Selmi, Luca ^a  

^a UNIVERSITY OF UDINE   (Italy)

^b INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

Clock generator; Clocking; Jitter; Mixed mode; Phase noise; Phase locked loop (PLL); Voltage controlled oscillator (VCO)

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; FREQUENCY SYNTHESIZERS; INTEGRATED CIRCUIT LAYOUT; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK GENERATORS; CLOCKING; MIXED-MODE; PHASE NOISE;

JITTER;

EID: 20444447199     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.848037     Document Type: Article

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