The effect of post-layout pin permutation on timing

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2005, Pages 41-50

  Ding, Yuzheng ^a   Suaris, Peter ^a   Chou, Nanchi ^a  

^a MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

FPGA; Logic synthesis; Placement; Timing Optimization

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; CONSTRAINT THEORY; LOGIC DESIGN; OPTIMIZATION; PATTERN RECOGNITION;

LOGIC ELEMENTS; LOGIC SYNTHESIS; PLACEMENT; TIMING OPTIMIZATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 20344365350     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1046192.1046199     Document Type: Conference Paper

References (20)

1. Stratix Device Handbook. Altera Corporation, 2004. (http://www.altera. com/literature/hb/stx/stratix_handbook.pdf)
2. Virtex-II Platform FPGA Handbook, Xilinx Corporation, 2002. (http://direct.xilinx.com/bvdocs/publications/ds031.pdf)
3. J. Cong and Y. Ding, "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays," ACM Trans. on Design Automation of Electronic Systems, Vol. 1, No. 2, pp. 145-204, Apr. 1996.
4. J. Cong, Y. Hwang and S. Xu, "Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections," Proc. ACM/IEEE Design Automation Conference, pp.373-378, June 1999.
5. J. Cong and Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Minimization in Lookup-table Based FPGA Designs," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 13, No. 1, pp.1-12, Jan. 1994.
6. J. Lin, A. Jagannathan and J. Cong, "Placement-Driven Technology Mapping For LUT-Based FPGAs," Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 121-126, Feb. 2003.
7. P. Suaris, L. Liu, Y. Ding and N. Chou, "Incremental Physical Resynthesis for Timing Optimization," Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp.99-108, Feb.2004.
8. 5/2 Algorithm for Maximum Matching in Bipartite Graphs," SIAM Journal on Computing, Vol. 2, No 4, pp 225-231, Aug. 1973.
9. R. Tarjan, Data Structures and Network Algorithms, SIAM Monograph, 1983.
10. H. Gabow and R. Tarjan, "Faster Scaling Algorithms for Network Problems." SIAM Journal on Computing, Vol. 18, No. 5, pp.1013-1036, Oct. 1989.
11. M. Fredman and R. Tarjan, "Fibonacci Heaps and Their Uses in Improved Network Optimization Algorithms," Journal of the ACM, Vol.34, No.3, pp.596-615, July 1987.
12. th Annual ACM Symposium on Theory of Computing, pp.514-527, 1988.
13. R. Ashenhurst, "The decomposition of switching functions," Proc. Int. Symp. Theory of Switching Functions, pp.74-116, Apr. 1957.
14. J. Cong and Y. Hwang, 'Boolean Matching for LUT-Based Logic Blocks With Applications to Architecture Evaluation and Technology Mapping," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp. 1077-1090, Sept. 2001.
15. J. Cong and Y. Ding, "Beyond The Combinatorial Limit in Depth Minimization For LUT-Based FPGA Designs," Proc. Int'l Conf. on Computer-Aided Design, pp. 634-639, Nov. 1993.
16. C. Legl, B. Wurth, and K. Eckl, "An implicit algorithm for support minimization during functional decomposition," Proc. European. Design and Test Conf., pp.412-417, Mar. 1996.
17. Logic Synthesis Benchmarks. http://www.vlsi.uvic.ca/downloads/benchmarks/ benchmarks.tar.Z
18. Precision RTL Synthesis Users Manual, Mentor Graphics Corporation, 2004. (http://www.mentor.com/precision/)
19. Quartus II Handbook, Altera Corporation, 2004. (http://www.altera.com/ literature/hb/qts/quartusii_handbook.pdf)
20. Precision Physical Synthesis Users Manual, Mentor Graphics Corporation, 2004. (http://www.mentor.com/precisionphysical/)