Technology mapping for FPGAs with nonuniform pin delays and fast interconnections

Proceedings - Design Automation Conference

Volumn , Issue , 1999, Pages 373-378

  Cong, Jason ^a   Hwang, Yean Yow ^a   Xu, Songjie ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN ALGEBRA; ELECTRIC NETWORK ANALYSIS; INTERCONNECTION NETWORKS; ITERATIVE METHODS;

TECHNOLOGY MAPPING PROBLEMS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0032630765     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/309847.309963     Document Type: Conference Paper

References (10)