Placement-driven technology mapping for LUT-based FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2003, Pages 121-126

  Lin, Joey Y ^a   Jagannathan, Ashok ^a   Cong, Jason ^a  

^a NONE

Author keywords

FPGA synthesis; Logic re synthesis; Mapping

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; OPTIMIZATION; TABLE LOOKUP;

CELL CONGESTION; INTERCONNECT DELAY; PLACEMENT DRIVEN MAPPING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0038349129     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/611835.611836     Document Type: Conference Paper

References (14)

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