Reference model based RTL verification: An integrated approach

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn , Issue , 2004, Pages 9-13

  Hung, William N N ^a   Narasimhan, Naren ^b  

^a Synplicity Inc   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL EQUIVALENCE VERIFICATION; FORMAL PROPERTY VERIFICATION (FPV); RTL DESIGNS; TEMPORAL LOGIC;

AUTOMATION; FUNCTIONS; INDUSTRIAL APPLICATIONS; MATHEMATICAL MODELS; PROBLEM SOLVING; SIGNAL PROCESSING;

COMPUTER AIDED DESIGN;

EID: 19944370138     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2004.1431221     Document Type: Conference Paper

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