Implication of assertion graphs in GSTE

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2, Issue , 2005, Pages 1060-1063

  Yang, Guowu ^a   Yang, Jin ^b   Hung, William N N ^b   Song, Xiaoyu ^a  

^a Portland State University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

BOOLEAN REASONING; DIGITAL SYSTEM; GENERALIZED SYMBOLIC TRAJECTORY EVALUATIONS; INDUSTRIAL CIRCUITS; MODEL SPECIFICATIONS; MODEL-BASED OPC; REACHABILITY;

GRAPHIC METHODS;

EID: 33745811567     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120824     Document Type: Conference Paper

References (7)

1. J. Yang and C. Seger, "Generalized Symbolic Trajectory Evaluation," Technical Report, 2002, Intel Corporation.
2. J, Yang and C. Seger, "lntroduction to Generalized SymboIic Trajectory Evaluation," IEEE Trans on VLSl Systems, I1(3), pp. 345-353,2003.
3. A. J. Hu, J. Casas, and J. Yang, "Efficient Generation of Monitor Circuits for GSTE Assertion Graphs," IEEE/ACM Inrernationol Confeence on Computer-Aided Design, 2003.
4. A. J. Hu, J. Casas, and J. Yang, "Reasoning about G S E Assertion Graphs," I2ih Advanced Research Working Conference on Correct Hardware Design and Veriifcation Meihods (CHARME), 2003.
5. C. Segar and R.E. Bryant, "Formal verification by symbolic evaluation of partially- ordered trajectories," Fonnal Methods in SysiemDesign, 6(2): 147-190, March 1995.
6. G. Yang and X. Song, "Formal Verification by Generalized Symbolic Trajectory Evaluation", Technical Report, Portland State University, 2004. http://www.ece.pdx.edu/~song/
7. W. N. N. Hung and N. Narasimhan, "Reference Model Based RTL Verification: An Integrated Approach", IEEE International High Level Design verification and Tesi Workshop (HLD fl), Sanama, California, November 2004.