메뉴 건너뛰기




Volumn 8, Issue 5, 2005, Pages

A novel isolation of pillarlike structures by CMP and etchback processes

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CHEMICAL MECHANICAL POLISHING; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; ETCHING; MICROPROCESSOR CHIPS; MOS DEVICES;

EID: 18944386474     PISSN: 10990062     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.1883979     Document Type: Article
Times cited : (8)

References (10)
  • 7
    • 84885186321 scopus 로고    scopus 로고
    • Silicon processing for the VLSI era
    • Lattice Press, Sunset Beach
    • S. Wolf, Silicon Processing for the VLSI Era, Vol. 4. - Deep Submicron Process Technology, Lattice Press, Sunset Beach (2002).
    • (2002) Deep Submicron Process Technology , vol.4
    • Wolf, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.