A 4Gb/s CMOS fully-differential analog dual delay-locked loop clock/data recovery circuit

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2003, Pages 559-562

  Mao, Zhiwei ^a   Szytnanski, Ted H ^a  

^a MCMASTER UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

AREA EFFICIENT; CLOCK-SAMPLING; CMOS TECHNOLOGY; COMMON MODE NOISE; CORRECTING FUNCTION; DELAY-LOCKED LOOPS; FULLY-DIFFERENTIAL; LOW POWER; POWER SUPPLY; POWER/GROUND BOUNCE; PROTOTYPE CIRCUITS; SMALL AREA; AREA-EFFICIENT; FULLY DIFFERENTIAL;

CMOS INTEGRATED CIRCUITS; CLOCKS;

CMOS INTEGRATED CIRCUITS; LOCKS (FASTENERS); PHASE LOCKED LOOPS;

EID: 18744388755     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2003.1301846     Document Type: Conference Paper

References (5)

1. M.-J. Edward Lee et al., "An 84-mW 4-Gb/s Clock and Data Recovery Circuit for Serial Link Applications," 2001 Symposium on VLSI Circuits Digest of Technical Papers, pp.149- 152,2001.
2. X. Maillard, et al, "A 900-Mb/s CMOS Data Recovery DLL Using Half-Frequency Clock" IEEE J. Solid-State Circuits, Vol. 37,No. 6,pp.711-715, Jun. 2002.
3. S.H. Lee, et al., " A 5 Gb/s 0.25um CMOS jitter tolerant variable-interval oversampling clock/data recovery circuit" ISSCC Digest of Technical Papers, pp.256-465,2002.
4. Behzad Razavi, "Monolithic phase-locked loops and clock recovery circuits theory and design" IEEE Press, NY, 1996.
5. Yongsarn Moon, et al. A 0.6-2.5-GBaud CMOS tracked 3x oversampling transceiver with dead-zone phase detection for robust clock/data recovery" IEEE J Solid-State Circuits, Vol. 36, pp. 1974-1983, Dec. 2001. (Pubitemid 34069264)