Minimizing average schedule length under memory constraints by optimal partitioning and prefetching

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 27, Issue 3, 2001, Pages 215-233

  Wang, Zhong ^a   O'Neil, Timothy W ^a,c   Sha, Edwin H M ^b,d,e,f  

^a University of Notre Dame   (United States)

^b The University of Texas at Dallas   (United States)

^c OHIO STATE UNIVERSITY   (United States)

^d NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^e Princeton University   (United States)

^f UNIVERSITY OF NOTRE DAME   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; DIGITAL SIGNAL PROCESSING; SCHEDULING;

AVERAGE SCHEDULE LENGTH; MEMORY CONSTRAINTS; OPTIMAL PARTITIONING; PREFETCHING;

CONSTRAINT THEORY;

EID: 0035280424     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008114531225     Document Type: Article

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