Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications

Proceedings - Design Automation Conference

Volumn , Issue , 2000, Pages 540-545

  Wang, Zhong ^a   Kirkpatrick, Michael ^a   Sha, Edwin Hsing Mean ^a  

^a UNIVERSITY OF NOTRE DAME   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; CONSTRAINT THEORY; DATA STRUCTURES; DIGITAL SIGNAL PROCESSING; GRAPH THEORY; THEOREM PROVING;

DATA SWAPPING; LOOP SCHEDULING; MEMORY MANAGEMENT TECHNIQUE; TWO LEVEL PARTITIONING;

DATA STORAGE EQUIPMENT;

EID: 0033701598     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/337292.337571     Document Type: Conference Paper

References (6)