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Volumn 4, Issue , 2004, Pages 2583-2588

High-performance decoders for regular and irregular repeat-accumulate codes

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DECODING; GRAPH THEORY; ITERATIVE METHODS; MAGNETIC RECORDING; MULTIMEDIA SYSTEMS; OPTIMIZATION; TELECOMMUNICATION SERVICES; WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 18144424752     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (15)

References (18)
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    • Near Shannon limit error-correcting coding and decoding: Turbo codes
    • C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding: Turbo codes," in IEEE Int. Conf. on Comm., 1993, pp. 1064-1070.
    • (1993) IEEE Int. Conf. on Comm. , pp. 1064-1070
    • Berrou, C.1    Glavieux, A.2    Thitimajshima, P.3
  • 2
    • 0016037512 scopus 로고
    • Optimal decoding of linear codes for minimizing symbol error rate
    • Mar.
    • L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal decoding of linear codes for minimizing symbol error rate," IEEE Trans. on Info. Theory, vol. 20. pp. 284-287, Mar. 1974.
    • (1974) IEEE Trans. on Info. Theory , vol.20 , pp. 284-287
    • Bahl, L.R.1    Cocke, J.2    Jelinek, F.3    Raviv, J.4
  • 4
    • 0035246127 scopus 로고    scopus 로고
    • Design of capacity-approaching irregular low-density parity-check codes
    • Feb.
    • T. Richardson, M. Shokrollahi, and R. Urbanke, "Design of capacity-approaching irregular low-density parity-check codes," IEEE Trans. on Info. Theory, vol. 47, no. 2, pp. 619-637, Feb. 2001.
    • (2001) IEEE Trans. on Info. Theory , vol.47 , Issue.2 , pp. 619-637
    • Richardson, T.1    Shokrollahi, M.2    Urbanke, R.3
  • 8
    • 0019608335 scopus 로고
    • A recursive approach to low complexity codes
    • Sep.
    • R. M. Tanner, "A recursive approach to low complexity codes," IEEE Trans. on Info. Theory, vol. IT-27, pp. 533-547, Sep. 1981.
    • (1981) IEEE Trans. on Info. Theory , vol.IT-27 , pp. 533-547
    • Tanner, R.M.1
  • 9
    • 3943066437 scopus 로고    scopus 로고
    • Design methods for irregular repeat-accumulate codes
    • Aug.
    • A. Roumy, S. Guemghar, G. Caire, and S. Verdu, "Design methods for irregular repeat-accumulate codes," IEEE Trans. on Info. Theory, vol. 50, no. 8, pp. 1711-1727, Aug. 2004.
    • (2004) IEEE Trans. on Info. Theory , vol.50 , Issue.8 , pp. 1711-1727
    • Roumy, A.1    Guemghar, S.2    Caire, G.3    Verdu, S.4
  • 13
    • 0000746201 scopus 로고    scopus 로고
    • Constructions of LDPC codes using Ramanujan graphs and ideas from Margulis
    • J. Rosenthal and P. O. Vontobel, "Constructions of LDPC codes using Ramanujan graphs and ideas from Margulis," in Proc. of the 38th Allerton Conf., 2000. pp. 248-257.
    • (2000) Proc. of the 38th Allerton Conf. , pp. 248-257
    • Rosenthal, J.1    Vontobel, P.O.2
  • 14
    • 0012799976 scopus 로고    scopus 로고
    • Construction of LDPC codes from Ramanujan graphs
    • Princeton University, Mar.
    • M. M. Mansour and N. R. Shanbhag, "Construction of LDPC codes from Ramanujan graphs," in Conf. on Info. Sciences and Systems, Princeton University, Mar. 2002.
    • (2002) Conf. on Info. Sciences and Systems
    • Mansour, M.M.1    Shanbhag, N.R.2
  • 15
    • 18144363708 scopus 로고    scopus 로고
    • On the architecture-aware structure of LDPC codes from generalized Ramanujan graphs and their decoder architectures
    • The Johns Hopkins University, Mar.
    • M. M. Mansour and N. R. Shanbhag, "On the architecture-aware structure of LDPC codes from generalized Ramanujan graphs and their decoder architectures," in Conf. on Info. Sciences and Systems, The Johns Hopkins University, Mar. 2003, pp. 215-220.
    • (2003) Conf. on Info. Sciences and Systems , pp. 215-220
    • Mansour, M.M.1    Shanbhag, N.R.2
  • 16
    • 0036954180 scopus 로고    scopus 로고
    • Low-power VLSI decoder architectures for LDPC codes
    • Aug.
    • M. M. Mansour and N. R. Shanbhag, "Low-power VLSI decoder architectures for LDPC codes," in ISLPED 2002, Monterey, CA, Aug. 2002, pp. 284-289.
    • (2002) ISLPED 2002, Monterey, CA , pp. 284-289
    • Mansour, M.M.1    Shanbhag, N.R.2
  • 17
    • 0036971714 scopus 로고    scopus 로고
    • Turbo decoder architectures for low-density' parity-check codes
    • Taipet, Taiwan, Nov.
    • M. M. Mansour and N. R. Shanbhag. "Turbo decoder architectures for low-density' parity-check codes," in Proc. IEEE Global Telecomm. Conf. 2002 (GLOBECOM'02). Taipet, Taiwan, Nov. 2002, pp. 1383-1388.
    • (2002) Proc. IEEE Global Telecomm. Conf. 2002 (GLOBECOM'02) , pp. 1383-1388
    • Mansour, M.M.1    Shanbhag, N.R.2
  • 18
    • 21644438346 scopus 로고    scopus 로고
    • A 1.6-Gbit/sec 2048-bit programmable and code-rate tunable LDPC decoder chip
    • Brest, France, Sep.
    • M. M. Mansour and N. R. Shanbhag. "A 1.6-Gbit/sec 2048-bit programmable and code-rate tunable LDPC decoder chip." in 3rd Int. Sympos. on Turbo Codes, Brest, France, Sep. 2003, pp. 137-140.
    • (2003) 3rd Int. Sympos. on Turbo Codes , pp. 137-140
    • Mansour, M.M.1    Shanbhag, N.R.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.