Lithography process optimization for 130nm poly gate mask and the impact of mask error factor

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4344, Issue 1, 2001, Pages 783-796

  Hsu, Stephen ^a   Shi, Xuelong ^a   Socha, Robert J ^a   Chen, J Fung ^a   Yee, Jason ^b   Ananth, Mohan ^b   Desai, Sunil ^b   Imamura, Philip H ^b   Sherrill, Micheal ^b   Tseng, Y C ^c   Chang, H A ^c   Kao, J F ^c   Tseng, Alex ^c   Liu, W J ^c   Chen, Anseime ^c   Lin, Arthur ^d   Kujten, Jan Pieter ^a   Jacobs, Eric ^a   Verhappen, Arjan ^a  

^a ASML US Inc   (United States)

^b KLA TENCOR CORPORATION   (United States)

^c UNITED MICROELECTRONICS CORPORATION   (Taiwan)

^d Grand Technology Inc   (United States)

Author keywords

ArF; Attenuated PSM; KrF; MEEF; Model OPC; Overlapped process windows; SB OPC

Indexed keywords

COMPUTER SIMULATION; ERRORS; GATES (TRANSISTOR); MASKS; OPTIMIZATION; PATTERN MATCHING;

MASK ERROR ENHANCEMENT FACTOR (MEEF);

PHOTOLITHOGRAPHY;

EID: 17944372929     PISSN: 0277786X     EISSN: None     Source Type: Journal    
DOI: 10.1117/12.436806     Document Type: Article

References (6)

1. Forbidden pitches for 130nm lithography and below
2. Status of ArF lithography for 130nm technology node
3. Optical proximity correction for intermediate-pitch features using sub-resolution scattering bars
4. Mask specifications for 193nm lithography
5. The mask error factor: Causes and implications for process latitude
6. Study of 193nm resist behaviour under SEM inspection: How to reduce line-width shrinking effect