Elimination of poly-Si gate depletion for Sub-65-nm CMOS technologies by excimer laser annealing

IEEE Electron Device Letters

Volumn 26, Issue 4, 2005, Pages 234-236

  Wong, Hiu Yung ^a   Takeuchi, Hideki ^a   King, Tsu Jae ^a   Ameen, Michael ^b   Agarwal, Aditya ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b AXCELIS TECHNOLOGIES   (United States)

Author keywords

Boron penetration; Excimer laser annealing (ELA); Gate depletion; Hafnium dioxide; High dielectric

Indexed keywords

BORON; CHEMICAL VAPOR DEPOSITION; CURRENT DENSITY; DIELECTRIC MATERIALS; EXCIMER LASERS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; MOS CAPACITORS; POLYSILICON; RAPID THERMAL ANNEALING;

BORON PENETRATION; EXCIMER LASER ANNEALING (ELA); GATE DEPLETION; HAFNIUM DIOXIDE;

CMOS INTEGRATED CIRCUITS;

EID: 17644419304     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.845502     Document Type: Article

References (11)

1. "International Technology Roadmap for Semiconductors,", San Jose, California, 2002.
2. H. Tseng, D. L. O'Meara, P. J. Tobin, V. S. Wang, G. Xin, R. Hegde, I. Y. Yang, P. Gilbert, R. Cotton, and L. Hebert, "Reduced gate leakage current and boron penetration of 0.18 μm 1.5 V MOSFETs using integrated RTCVD oxynitride gate dielectric," in IEDM Tech. Dig., 1998, pp. 793-796.
3. C. Min, P. V. Voorde, M. Cox, and W. M. Greene, "Boron diffusion and penetration in ultrathin oxide with poly-Si gate," IEEE Electron Device Lett., vol. 19, no. 3, pp. 291-293, Mar. 1998.
4. F. Ootsuka, H. Ozaki, T. Sasaki, K. Yamashita, H. Takada, N. Izumi, and Y. Nakagawa, "Ultra-low thermal budget CMOS process for 65-nm-node low-operation-power applications," in IEDM Tech. Dig., 2003, pp. 27.7.1-27.7.4.
5. B. Yu, Y. Wang, H. Wang, Q. Xiang, C. Riccobene, S. Talwar, and M. Lin, "70 nm MOSFET with ultra-shallow, abrupt, and super-doped S/D extension implemented by laser thermal process (LTP)," in IEDM Tech. Dig., 1999, pp. 509-512.
6. Y. Takamura, S. H. Jain, P. B. Griffin, and J. D. Plummer, "Thermal stability of dopants in laser annealed silicon," J. Appl. Phys., vol. 92, pp. 230-234, 2002.
7. Y.F. Chong, H.-J. L. Gossmann, K.-L. Pey, M. O. Thompson, A. T. S. Wee, and C. H. Tung, "Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices," IEEE Electron Device Lett. vol. 24, no. 6, pp. 669-676, Jun. 2003.
8. R. F. Wood and G. E. Giles, "Macroscopic theory of pulsed-laser annealing. I. Thermal transport and melting," Phy. Rev. B, vol. 23, pp. 2923-2942, 1981.
9. S. Pantelides, Deep Centers in Semiconductors. New York: Gordon and Breach, 1992, pp. 177-211.
10. H. Takeuchi, H. Y. Wong, D. Ha, and T.-J. King, "Impact of oxygen vacancies on high-κ gate stack engineering," in IEDM Tech. Dig., 2004, pp. 829-832.
11. H.Y. Wong, H. Takeuchi, T.-J. King, M. Ameen, and A. Agarwal, "Reduced poly-Si gate depletion effect by pulsed excimer laser annealing," in Proc. Advanced Short-Time Thermal Processing Si-Based CMOS Devices II 2004, pp. 205-215.