Analysis of the back gate effect on the breakdown behaviour of SOI LDMOS transistors

ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

Volumn , Issue , 2004, Pages 253-256

  Schwantes, Stefan ^a   Florian, Tobias ^a   Graf, Michael ^a   Dietz, Franz ^a   Dudek, Volker ^a  

^a Atmel Germany GmbH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC BREAKDOWN; ELECTRIC POTENTIAL; ELECTRODES; EPITAXIAL GROWTH; MATHEMATICAL MODELS; POISSON EQUATION; SILICON ON INSULATOR TECHNOLOGY; TRANSISTORS;

BACK GATE EFFECTS; SMART POWER APPLICATIONS; SOI LDMOS TRANSISTORS; TWO DIMENSIONAL DEVICE SIMULATORS;

MOS DEVICES;

EID: 17644411129     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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