CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance

ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

Volumn , Issue , 2004, Pages 221-224

  Kunz, V D ^a,c   De Groot, C H ^a   Gili, E ^a   Uchino, T ^a   Hall, S ^b   Ashburn, P ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^b UNIVERSITY OF LIVERPOOL   (United Kingdom)

^c ON SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ION IMPLANTATION; LITHOGRAPHY; LOGIC GATES; MASKS; NAND CIRCUITS; OXIDATION; POLYSILICON;

FILLER LOCAL OXIDATION (FILOX) PROCESS; GATE LITHOGRAPHY; PARASITIC CAPACITANCE;

MOSFET DEVICES;

EID: 17644383735     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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6. Kunz V.D., Uchino T., de Groot C.H., Ashburn P. et al.; Reduction pf Parasitic Capacitance in Vertical MOSFETs by Spacer Oxidation; IEEE Trans Electron Devices 2003; 50(6); p. 1487-1493
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