Investigations on possible occurrence of ballistic transport in different NMOS architectures

ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

Volumn , Issue , 2004, Pages 237-240

  Clerc, R ^a   Ferrier, M ^a,b   Dauge F ^a   Ghibaudo, G ^a   Boeuf, F ^b   Skotnicki, T ^b  

^a IMEP LAHC   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER MOBILITY; COMPUTER SIMULATION; ELECTRIC RESISTANCE; ELECTRON SCATTERING; FERMI LEVEL; GATES (TRANSISTOR); SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; ULTRATHIN FILMS;

BALLISTIC TRANSPORT; DRAIN VOLTAGE; NMOS DEVICES; QUANTUM QUANTIZATION;

MOS DEVICES;

EID: 17644365480     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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