Designing a via-configurable regular fabric

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2004, Pages 423-426

  Ran, Yajun ^a   Marek Sadowska, Malgorzata ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; LOGIC DESIGN; LOGIC GATES; SIGNAL PROCESSING; TABLE LOOKUP; TRANSISTORS;

CIRCUIT MAPPING; INTER-BLOCK CONNECTIONS; INTRA-BLOCK CONNECTIONS; VIA-CONFIGURABLE BLOCK (VCB);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 17044411299     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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4. B. Hu, H. Jiang, Q. Liu, and M. Marek-Sadowska, "Synthesis and placement flow for gain-based programmable regular fabrics," ISPD'03, pp. 197-203.
5. Y. Ran and M. Marek-Sadowska, "On designing via-configurable cell blocks for regular fabrics," DAC'04, to appear.
6. L. Pileggi et al., "Exploring regular fabrics to optimize the performance-cost trade-off," DAC'03, pp. 782-787.
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