Design of low-power libraries

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 1998, Pages 175-180

  Piguet, C ^a  

^a CSEM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; GRAPH THEORY;

DESIGN SPEED; INTERNAL NODES; LOW POWER; PARASITIC CAPACITANCE; SIGNAL TRANSITION GRAPHS;

DESIGN; INTEGRATED CIRCUIT LAYOUT;

LOW-POWER STANDARD CELL LIBRARIES; SIGNAL TRANSITION GRAPHS (STG);

EID: 0032273279     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1998.814857     Document Type: Conference Paper

References (25)

1. A. Bellouar et al. "Low-Power Digital VLSI Design, Circuits and Systems", Kluwer Academic Publishers, Boston, 1995.
2. M. Lowy, J. J. Thieman "Ultra-Low Power Digital CMOS Circuits Techniques", IEEE VLSI Signal Proc V, K. Yao, R. Jain, W. Przytula, editors, 1992, pp. 31-40.
3. A. P. Chandrakasan, S. Sheng, R. W. Brodersen, "Low-Power CMOS Digital Design" IEEE J. of Solid-State Circuits, Vol. 27, No 4, April 1992, pp. 473-484.
4. Kazuo Yano et al. "A 3.8ns CMOS 16×16b Multiplier Using Complementary Pass-Transistor Logic" JSSC-25, No 2, April 1990, pp. 388.
5. L. G. Heller et al. "Cascode Voltage Switch Logic : A Differential CMOS Logic Family", Proc. ISSCC 1984, pp. 16-17, San Francisco, CA
6. J. A. Pretorius et al, "Latched Domino CMOS Logic" IEEE JSSC Vol SC-21, No 4, August 1986, pp. 514-522.
7. J-M. Masgonty et al. "Technology-and Power-Supply-Independent Cell Library" IEEE CICC91, May 12-15, 1991, San Diego, CA, USA, Conf. 255
8. R. Zimmermann, R. Gupta, "Low-Power Logic Styles: CMOS vs CPL", ESSCIRC'96, pp. 112-115, Neuchâtel Switzerland, Sept. 17-19, 1996.
9. C. Piguet et al. "Low-Power Design of a Standard Cell Library", Low-Voltage Low-Power Workshop during ESSCIRC'95, Lille, France, September 22, 1995.
10. J-M. Masgonty et al. "Branch-Based Digital Cell Libraries" EURO-ASIC'91, 27-31 Mai 1991, Paris.
11. C. Piguet et al. "Low-Power Low-Voltage Digital CMOS Cell Design", Proc. PATMOS'94, Oct. 17-19, 1994 Barcelona, Spain, pp. 132-139.
12. T. K. Liu, "Synthesis Algorithms for 2-levels MOS Networks" IEEE Trans, on Comput. C-24, No 1, Jan. 1975.
13. D. Liu, C. Svensson, "Trading Speed for Low Power by Choice of Supply and Threshold Voltages", JSSC-28, No 1, Jan. 1993, pp. 10-17. pp. 514-522.
14. A. Kondratyev et al. "Technology mapping for Speed-Independent Circuits: Decomposition and Resynthesis", ASYNC'97, Eindhoven, The Netherlands, pp. 240-253.
15. L. Lavagno et al. "Algorithms for Synthesis and Testing of Asynchronous Circuits", Kluwer Academic Publ., 1993.
16. A. Kondratyev et al. "Basic Gate Implementation of Speed-Independent Circuits", 31st Design Automation Conf. DAC, 1994, pp. 56-62.
17. C. Piguet, "Supplementary Condition for STG-designed Speed-Independent Circuits", accepted for publication in Electronics Letters, April 1998
18. C. Piguet, "Logic Synthesis of Race-Free Asynchronous CMOS Circuits", JSSC-26, No 3, March 1991, pp. 271-380.
19. C. Piguet, "Synthesis of Asynchronous CMOS Circuits with Negative Gates", Journal of Solid-State Devices and Circuits, Vol. 5, No 2, Brazilian Microelectronics Society, July 1997, pp. 12-20.
20. P. Vanbekbergen et al. "A Generalized State Assignment Theory for Transformations on Signal Transition Graphs", Proc. International Conf. on Computer-Aided-Design ICCAD, pp. 112-117, 1992.
21. J. Yuan, C. Svensson, "High-Speed CMOS Circuit Technique", JSSC SC-24, pp. 62-70, 1989.
22. C. Piguet et al. "Low-Power Low-Voltage Digital CMOS Cell Design", PATMOS'94, Oct. 17-19, Barcelona, Spain, pp. 132-139.
23. C. Piguet, V. von Kaenel, "Logic Synthesis of a PLL Phase Frequency Detector", IEE Proc. Computers and Digital Techniques, Vol. 144, No 6, November 1997, pp. 381-385.
24. V. von Kaenel et al. "A 600 MHz CMOS PLL Microprocessor Clock Generator with a 1.2 GHz VCO", ISSCC'98, San Francisco, February 5-7, 1998, Conf. 25.1
25. R. Hossain et al. "Low-Power Design Using Double Edge Triggered Flip-Flops", IEEE Trans, on Very Large Scale Integr. Syst. Vol. 2, No 2, June 1994, pp. 261.