Evaluating high leakage effects of low Vth circuits using high Vth devices

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2004, Pages 241-244

  Miyazaki, Takayuki ^a   Sakurai, Takayasu ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; MOSFET DEVICES; NETWORKS (CIRCUITS); OSCILLATORS (ELECTRONIC); THRESHOLD VOLTAGE;

BODY BIAS; LEAKAGE EMULATORS; PMOS; PN JUNCTIONS;

LEAKAGE CURRENTS;

EID: 3042611443     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. 2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme," in ISSCC Dig. Tech. Papers, pp. 166-167, Feb. 1996.
2. S. Narendra, A. Keshavarzi, B. A. Bloechel, S. Borkar, and V. De, "Forward Body Bias for Microprocessors in 130-nm Technology Generation and Beyond," IEEE. Journal of Solid-State Circuits, vol.38, no.5, pp. 696-701, May 2003.
3. L. Wei, Z. Chen, K. Roy, M. C. Johnson, Y. Ye, and V. K. De, "Design and Optimization of Dual-Threshold Circuits for Low-Voltage Low-Power Applications," IEEE Trans. On Very Large Scale Integration(VLSI) Systems, vol. 7, no. 1, Mar. 1999.
4. K. S. Min and T. Sakurai, "Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era," in ISSCC Dig. Tech. Papers, pp.400-401, Feb. 2003.