Positive Oxide Charge-Enhanced Read Disturb in a Localized Trapping Storage Flash Memory Cell

IEEE Transactions on Electron Devices

Volumn 51, Issue 3, 2004, Pages 434-439

  Tsai, Wen Jer ^a,b   Yeh, Chih Chieh ^a,b   Zous, Nian Kai ^a   Liu, Chen Chin ^a   Cho, Shih Keng ^a   Wang, Tahui ^a,b   Pan, Samuel C ^a   Lu, Chin Yuan ^a  

^a MACRONIX INTERNATIONAL CO LTD   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Cycling induced oxide charges; Flash EEPROM; Hot carrier effect; MXVAND; NROM; PHINES; Poly silicon oxide nitride oxide silicon (SONOS); Positive charge assisted electron tunneling; Read disturb; Threshold voltage (Vt) instability; Tunnel detrapping

Indexed keywords

ELECTRIC CURRENTS; ELECTRON TUNNELING; HOT CARRIERS; LOW TEMPERATURE EFFECTS; OPTIMIZATION; POLYSILICON; SEMICONDUCTOR DOPING; SILICA; THRESHOLD VOLTAGE;

CYCLING-INDUCED OXIDE CHARGES; FLASH EEPROM; MXVAND; NROM; PHINES; READ DISTURB; TUNNEL DETRAPPING;

FLASH MEMORY;

EID: 1642317838     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.822869     Document Type: Article

References (21)

1. T. K. Chan, K. K. Young, and C. Hu, "A true single-transistor oxide-nitride-oxide EEPROM device," IEEE Electron Device Lett., vol. EDL-8, pp. 93-95, 1987.
2. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "NROM: a novel localized trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Lett., vol. 21, pp. 543-545, Nov. 2000.
3. W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, and C.-Y. Lu, "Data retention behavior of a SONOS type two-bit storage Flash memory cell," in IEDM Tech. Digest, 2001, pp. 719-722.
4. H. Tomiye, T. Terano, K. Nomoto, and T. Kobayashi, "A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applied source-side hot-electron injection," in Symp. VLSI Tech. Dig., 2002, pp. 206-207.
5. C. C. Yeh, W. J. Tsai, M. I. Liu, T. C. Lu, S. K. Cho, C. J. Lin, T. Wang, S. Pan, and C.-Y. Lu, "PHINES: a novel low power program/erase, small pitch, 2-bit per cell Flash memory," in IEDM Tech. Dig., 2002, pp. 931-934.
6. M. H. White, D. Adams, and J. Bu, "On the go with SONOS," IEEE Circuits Devices Mag., vol. 16, pp. 22-31, 2000.
7. M. K. Cho and D. M. Kim, "High performance SONOS memory cells free of drain turn-on and over-erase: Compatibility issue with current Flash technology," IEEE Electron Device Lett., vol. 21, pp. 399-401, Oct. 2000.
8. Y. Roizin, M. Cutman, E. Aloni, V. Kairys, and P. Zisman, "Retention characteristics of microFlash memory (activation energy of traps in the ONO stack)," in Proc. Non-Volatile Semiconductor Memory Workshop, 2001, pp. 128-129.
9. E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, "Electron discharge model of locally-trapped charge in oxide-nitride-oxide (ONO) gate for NROMTM nonvolatile semiconductor memory device," in Proc. Solid State Devices Materials Conf., 2001, pp. 534-535.
10. W. J. Tsai, S. H. Gu, N. K. Zous, C. C. Yeh, C. C. Liu, C. H. Chen, T. Wang, S. Pan, and C.-Y. Lu, "Cause of data retention loss in a nitride-based localized trapping storage Flash memory cell," in Proc. Int. Reliabil. Phys. Symp., 2002, pp. 34-38.
11. M. Jannai, "Data retention, endurance and acceleration factors of NROM devices," in Proc. Int. Reliabil. Phys. Symp., 2003, pp. 502-505.
12. M. Tanaka, S. Saida, Y. Mitani, I. Mizushima, and Y. Tsunashima, "Highly reliable MONOS devices with optimized silicon nitride film having deuterium terminated charge traps," in IEDM Tech. Digest, 2002, pp. 237-240.
13. 3 as charge trapping layer," in Proc. Non-Volatile Semiconductor Memory Workshop, 2003, pp. 60-61.
14. W. J. Tsai, C. C. Yeh, N. K. Zou, C. C. Liu, S. K. Cho, C. H. Chen, T. Wang, S. Pan, and C.-Y. Lu, "Hot carrier enhanced read disturb and scaling effects in a localized trapping storage SONOS type Flash memory cell," in Proc. Solid State Devices and Materials Conf., 2002, pp. 164-165.
15. S. Manzini and A. Modelli, "Tunneling discharge of trapped holes in silicon dioxide," in Insulating Films on Semiconductors. Amsterdam, The Netherlands: Elsevier, 1983, pp. 112-115.
16. T. Wang, N. K. Zous, J. L. Lai, and C. Huang, "Hot hole Stress Induced Leakage Current (SILC) transient in tunnel oxides," IEEE Electron Device Lett., vol. 19, pp. 411-413, Nov. 1998.
17. T. Wang, N. K. Zous, and C. C. Yeh, "Role of positive trapped charge in stress-induced leakage curret for Flash EEPROM devices," IEEE Trans. Electron Devices, vol. 49, pp. 1016-1910, Nov. 2002.
18. D. Esseni, L. Selmi, E. Sagiorgi, R. Bez, and B. Ricco, "Temperature dependence of gate and substrate currents in the CHE crossover regime," IEEE Electron Device Lett., vol. 16, pp. 506-508, Dec. 1995.
19. C. T. Swift, G. L. Chindalore, K. Harber, T. S. Harp, A. Holfer, C. M. Hong, P. A. Ingersoll, C. B. Li, E. J. Prinz, and J. A. Yater, "An embedded 90 nm SONOS nonvalatile memory utilizing hot electron programming and uniform tunnel erase," in IEDM Tech. Dig., pp. 927-930.
20. C. C. Yeh, W. J. Tsai, T. C. Lu, S. K. Cho, T. Wang, S. Pan, and C. Y. Lu, "A modified read scheme to improve read disturb and second bit effect in a scaled MXVAND Flash memory cell," in Proc. Non-Volatile Semiconductor Memory Workshop, 2003, pp. 44-45.
21. T. Wang et al., "Reliability models of data retention and read-disturb in 2-bit nitride storage Flash memory cells," in IEDM Tech. Dig., 2003, pp. 169-192.