On per-test fault diagnosis using the X-fault model

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 633-640

  Wen, Xiaoqing ^a   Miyoshi, Tokiharu ^a   Kajihara, Seiji ^a   Wang, Laung Terng ^b   Saluja, Kewal K ^c   Kinoshita, Kozo ^d  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^b SYNTEST TECHNOLOGIES INC   (United States)

^c University of Wisconsin Madison   (United States)

^d OSAKA GAKUIN UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER SOFTWARE; DEFECTS; ELECTRIC NETWORK ANALYSIS; FAILURE ANALYSIS; GRAPH THEORY; MATHEMATICAL MODELS;

FAULT DIAGNOSIS; HARDWARE-BASED LOCALIZATION; SOFTWARE-BASED LOCALIZATION; X-FAULT MODEL;

ELECTRIC FAULT CURRENTS;

EID: 16244410462     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. M. Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990.
2. ITRS Roadmap: Test & Test Equipment, 2003 Edition, http://public.itrs.net/, 2003.
3. D. Lavo, T. Larrabee, and B. Chess, "Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis", Proc. Intl. Test Conf., pp. 611-619, 1996.
4. C. Beh, K. Arya, C. Radke, and K. Torku, "Do Stuck Fault Models Reflect Manufacturing Defects", Proc. Intl. Test Conf., pp. 35-42, 1982.
5. S. D. Millman, E.J. McCluskey, and J.M. Acken, "Diagnosing CMOS Bridging Faults with Stuck-At Fault Dictionaries", Proc. Intl. Test Conf., pp. 860-870, 1990.
6. P. Maxwell and R. Aiken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds", Proc. Intl. Test Conf., pp. 63-72, 1993.
7. W. Mao and R. K. Gulati, "QUIETEST: A Quiescent Current Testing Methodology for Detecting Short Faults", Proc. ICCAD'90, pp. 280-283, Nov. 1990.
8. S. Huang, "Speeding Up the Byzantine Fault Diagnosis Using Symbolic Simulation", Proc. VLSI Test Symp., pp. 193-198, 2002.
9. M. Abramovici and M. Breuer, "Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis", IEEE Trans. on Comp., vol. 29, no. 6, pp. 451-460, 1980.
10. H. Cox and J. Rajski, "A Method of Fault Analysis for Test Generation and Fault Diagnosis", IEEE Trans. on Computer-Aided Design, vol. 7, no. 7, pp. 813-833, 1988.
11. H. Takahashi, K.O. Boateng, K.K Saluja, and Y. Takamatsu, "On Diagnosing Multiple Stuck-At Faults Using Multiple and Single Fault Simulation", IEEE Trans. on Computer-Aided Design, vol. 21, no. 5, pp. 362-368, 2002.
12. S. Venkataraman and S. Drummonds, "POIROT: A Logic Fault Diagnosis Tool and Its Applications", Proc. Intl. Test Conf., pp. 253-262, 2000
13. J. Waicukauski and E. Lindbloom, "Failure Diagnosis of Structured Circuits", IEEE Design and Test of Comp., vol. 6, no. 4, pp. 49-60, 1989.
14. T. Bartenstein, D. Heaberlin, L. Huisman, and D. Sliwinski, "Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm", Proc. Intl. Test Conf., pp. 287-296, 2001.
15. D. Lavo, I. Hartanto, and T. Larrabee, "Multiplets, Models and the Search for Meaning", Proc. Intl. Test Conf., pp. 250-259, 2002.
16. X. Wen, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "Fault Diagnosis for Physical Defects of Unknown Behaviors", Proc. Asian Test Symp., pp. 236-241, 2003.
17. X. Wen, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "Fault Diagnosis for Static CMOS Circuits", Proc. Asian Test Symp., pp. 282-287, 1997.
18. F. Brglez and H. Fujiwara, "A Neutral Netlist of Combinational Benchmark Circuits and a Target Translator in FORTRAN", Proc. Intl. Symp. on Circuits and Systems, 1985.