SEPAS: A highly accurate energy-efficient branch predictor

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 38-43

  Baniasadi, Amirali ^a   Moshovos, Andreas ^b  

^a UNIVERSITY OF VICTORIA   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

Author keywords

High Performance Processors; Power Aware Branch Prediction; Selective Predictor Access

Indexed keywords

HIGH-PERFORMANCE PROCESSORS; POWER DISSIPATION; POWER-AWARE BRANCH PREDICTION; SELECTIVE PREDICTOR ACCESS (SEPAS);

COMPUTER SOFTWARE; COSTS; ENERGY DISSIPATION; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; PERFORMANCE;

ENERGY EFFICIENCY;

EID: 16244380188     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M.R. Stan. Power Issues Related to Branch Prediction. In Proc. of International Symposium on High-Performance Computer Architecture, Feb. 2002.
2. P.Chang, M.Evers and Y.N. Patt, Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference. In Proc. of International Conference on Parallel Architectures and Compilation Techniques. 1996.
3. D.A.Jimenez, S.W.Keckler, C. Lin, The Impact of Delay on the Design of Branch Predictors. In Proc. of International Symposium on Microarchitecture, Dec. 2000.
4. A.N.Eden and T.Mudge, The YAGS Branch Prediction Scheme, In Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture, Nov. 1998
5. D. Brooks, V. Tiwari M. Martonosi, Wattch: A Framework for Architectural-Level Power Analysis and Optimizations, In Proc. of International Symposium on Computer Architecture, 2000.
6. A. Baniasadi, A. Moshovos, Branch Predictor prediction a Power-Aware Branch Predictor for High-Performance Processors. In Proc. of International Conference on Computer Design, Sep. 2002.
7. P.-Y. Chang, E. Hao, and Y.N. Part. Alternative Implementations of Hybrid Branch Predictors. In Proc. of the 28th Annual International Symposium on Microarchitecture. Dec. 1995.
8. S. McFarling. Combining Branch Predictors. Tech. Note TN-36, DECWRL, Jun. 1993.
9. T.A. Diep, C. Nelson, and J.P. Shen. Performance Evaluation of the PowerPC 620 microarchitecture. In Proc. of International Symposium on Computer Architecture, Jun. 1995.
10. D. Leibholz and R. Razdan. The Alpha 21264: A 500 MHz Out-of-order Execution Microprocessor. COMPCON97, 1997.
11. C.H. Perleberg and A.J. Smith. Branch Target Buffer Design and Optimization. In IEEE Transactions of Computers, April 1993.
12. S. Wilton and N. Jouppi. An Enhanced Access and Cycle Time Model for On-chip Caches. In WRL Research Report 93/5, DEC Western Research Laboratory, 1994.
13. D. C. Burger and T. M. Austin. The SimpleScalar tool set,version 2.0. Computer Architecture News, 25(3): 13-25, Jun. 1997.
14. Digital Semiconductor. DECchip 21064/21064A Alpha AXP Microprocessors: Hardware Reference Manual, Jun. 1994.
15. Digital Semiconductor. Alpha 21164 Microprocessor: Hardware Reference Manual, Apr. 1995.
16. A.Seznec, S.Felix, V.Krishnam and Y.Sazeides. Design Tradeoffs for the Alpha EV8 conditional branch predictor. In Proc. of the 29th International Symposium on Computer Architecture, May 2002
17. M.C Huang, D. Chaver, L. Pinuel, M. Prieto, F. Tirado. Customizing The Branch Predictor To Reduce Complexity And Energy Consumption, In IEEE micro. Sep. 2003
18. J.E. Smith. A Study of Branch Prediction Strategies. In Annual International Symposium on Computer Architecture, May 1981
19. Z. Hu, P. Juang, K.Skadron, D.Clark and M. Martonosi. Applying Decay Strategies to Branch Predictors for Leakage Energy Savings. In Proc. of International Conference on Computer Design, Sep. 2002