Benchmark-based design strategies for single chip heterogeneous multiprocessors

Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, CODES+ISSS 2004

Volumn , Issue , 2004, Pages 54-59

  Paul, JoAnn M ^a   Thomas, Donald E ^a   Bobrek, Alex ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Benchmarking; Heterogeneous Multiprocessing; Scenario oriented Design; Systems on Chips (SoCs)

Indexed keywords

BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; EMBEDDED SYSTEMS; GENERAL PURPOSE COMPUTERS; INPUT OUTPUT PROGRAMS; MICROPROCESSOR CHIPS; MULTIPROCESSING PROGRAMS; VLSI CIRCUITS;

DESIGN AUTOMATION (DA); HETEROGENEOUS MULTIPROCESSING; SCENARIO-ORIENTED DESIGN; SYSTEMS-ON-CHIPS (SOC);

MULTIPROCESSING SYSTEMS;

EID: 16244379870     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016720.1016736     Document Type: Conference Paper

References (16)

1. Special Issue 2002 on Ubiquitous Computing in Communications of the ACM.
2. W. Wolf. "How many system architectures?" Computer, March 2003, pp. 93-95.
3. International Technology Roadmap for Semiconductors 2003 http://public.itrs.net/
4. J. Paul. "Programmers' Views of SoCs," CODES-ISSS, 2003.
5. www.openmp.org
6. K. Keutzer, et. al. "System-Level Design: Orthogonalization of Concerns and Platform-Based Design," IEEE TCAD, p. 1523-1543, Dec. 2000.
7. http://www.simplescalar.com
8. http://www.spec.org
9. http://www.eembc.com
10. http://www.bdti.com
11. M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown. "MiBench: A free, commercially representative embedded benchmark suite." Proc. 4th Workshop on Workload Characterization, pp. 1-12. 2001.
12. C. Lee, M. Potkonjak, and W. Mangione-Smith. MediaBench: A tool for evaluating and synthesizing multimedia and communications systems. ISCA 1997. pp. 330-335.
13. F. Karim, A. Mellan, B. Stramm, T. Abdelrahman, U. Aydonat. "The Hyperprocessor: a Template Architecture for Embedded Multimedia Applications." WASP 2003.
14. K. Lahiri, K., A. Raghunathan, A., et. al. "LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. DAC 2001.
15. A. Bobrek, J. Pieper, J. Nelson, J. Paul, D. Thomas, "Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach," DATE, 2004.
16. www.gnu.org/software/gdb/