An automatic test pattern generation framework for combinational threshold logic networks

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 540-543

  Gupta, Pallav ^a   Zhang, Rui ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION (ATPG); COMBINATIONAL THRESHOLD LOGIC NETWORKS; RESONANT TUNNELING DIODES (RTD); THRESHOLD FUNCTION;

AUTOMATIC TESTING; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ELECTRONIC EQUIPMENT TESTING; FUNCTIONS; LOGIC CIRCUITS; LOGIC GATES; RESONANT TUNNELING; TUNNEL DIODES;

THRESHOLD LOGIC;

EID: 15844371876     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2004.1347974     Document Type: Conference Paper

References (10)

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