Full-chip power-supply noise: The effect of on-chip power-rail inductance

International Journal of High Speed Electronics and Systems

Volumn 12, Issue 2, 2002, Pages 573-582

  Fok, C W ^a   Pulfrey, D L ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; FLIP CHIP DEVICES; INDUCTANCE; INFRARED RADIATION; MOSFET DEVICES; SEMICONDUCTING SILICON; SPURIOUS SIGNAL NOISE;

FULL CHIP POWER NETWORKS; POWER SUPPLY NOISE (PSN);

MICROPROCESSOR CHIPS;

EID: 1542789172     PISSN: 01291564     EISSN: None     Source Type: Journal    
DOI: 10.1142/S0129156402001472     Document Type: Conference Paper

References (12)

1. P. Zarkesh-Ha and J.D. Meindl, "Optimum On-Chip Power Distribution Networks for Gigascale Integration (GSI)", Proc. IEEE Intl. Interconnect Technology Conf. (IITC), 2001, pp. 125-127.
2. R. Panda, D. Blaauw, R. Chaudhry, V. Zolotov, B. Young, and R. Ramaraju, "Model and Analysis for Combined Package and On-Chip Power Grid Simulation", Proc. Intl. Symp. on Low Power Electronics and Design (ISLPED), 2000, pp. 179-184.
3. P. Heydari and M. Pedram, "Analysis and Optimization of Ground Bounce in Digital CMOS Circuits", Proc. IEEE Intl. Conf. on Computer Design (ICCD), 2000, pp. 121-126.
4. W.S. Song and L.A. Classer, "Power Distribution Techniques for VLSI Circuits", IEEE J. Solid-State Circuits, SC-9 (1986) 150-156.
5. B. Krauter and L.T. Pileggi, "Generating Sparse Partial Inductance Matrices with Guaranteed Stability", IEEE/ACM Intl. Conf. Computer Aided Design (ICCAD),1995, pp. 45-52.
6. R. Chaudhry, R. Panda, T. Edwards and D. Blaauw, "Design and Analysis of Power Distribution Networks with Accurate RLC Models", Proc. 13th International Conference on VLSI Design, 2000, pp. 151-155.
7. H.H. Chen and J.S. Neely, "Interconnect and Circuit Modeling Techniques for Full-Chip Power Supply Noise Analysis", IEEE Trans. Comp., Packag., Manufact. Technol., 21 (1998) pp. 446-452.
8. M. Benoit, S. Taylor, D. Overhauser and S. Rochel, "Power Distribution in High-Performance Design", Proc. Intl. Symp. on Low Power Electronics and Design (ISLPED), 1998, pp. 274-278.
9. D. Sylvester and K. Keutzer, "Getting to the Bottom of Deep Submicron", IEEE/ACM Intl. Conf. Computer Aided Design (ICCAD), 1998, pp. 203-211.
10. S. Gong, H. Hentzell, S.-T, Persson, H. Hesselbom, B. Lofstedt and M. Hansen, "Pack-aging impact on switching noise in high-speed digital systems", IEE Proc.-Circuits Devices Syst., 145 (1998) pp. 446-452.
11. S. Lin and N. Chang, "Challenges in Power-Ground Integrity", IEEE/ACM Intl. Conf. Computer Aided Design (ICCAD), 2001, pp. 651-654.
12. S. Bobba and I.N. Hajj, "Simultaneous Switching Noise in CMOS VLSI Circuits", Southwest Symp. on Mixed-signal Design, 1999, pp. 15-20.