Detailed investigation of geometrical factor for pseudo-MOS transistor technique

IEEE Transactions on Electron Devices

Volumn 52, Issue 3, 2005, Pages 406-412

  Komiya, Kenji ^a   Bresson, Nicolas ^b,c   Sato, Shingo ^a   Cristoloveanu, Sorin ^b   Omura, Yasuhisa ^a  

^a KANSAI UNIVERSITY   (Japan)

^b IMEP LAHC   (France)

^c PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

Carrier mobility; Geometrical factor; Probe pressure; Pseudo MOS ( MOSFET) transistor; Silicon on insulator (SOI)

Indexed keywords

CARRIER MOBILITY; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; PRESSURE EFFECTS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS;

GEOMETRICAL FACTOR; PROBE PRESSURE; PSEUDO MOSFET;

MOSFET DEVICES;

EID: 15044345754     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.843970     Document Type: Article

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