Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface

IEEE Electron Device Letters

Volumn 23, Issue 6, 2002, Pages 363-365

  Ker, Ming Dou ^a,b   Chuang, Chien Hui ^b  

^a IEEE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Electrostatic discharge (ESD); ESD protection; Mixed voltage I O buffer; Silicon controlled rectifier (SCR)

Indexed keywords

ELECTROSTATIC DISCHARGE; GATE OXIDE;

BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC DISCHARGES; ELECTROSTATICS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MOSFET DEVICES;

THYRISTORS;

EID: 0036609869     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2002.1004236     Document Type: Letter

References (12)

1. Accelerated gate-oxide breakdown in mixed-voltage I/O circuits
2. An empirical model for device degradation due to hot-carrier injection
3. High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay
4. A 3/5 V compatible I/O buffer
5. High-voltage-tolerant I/O buffers with low-voltage CMOS process
6. 5.5-V I/O in a 2.5-V 0.25-μm CMOS technology
7. Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI
8. ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration
9. A low-voltage triggering SCR for on-chip ESD protection at output and input pads
10. ESD protection design for mixed-voltage I/O buffer by using stacked-NMOS triggered SCR device