Backside failure analysis and case studies for Cu/Low k technology

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2004, Pages 127-134

  Wu, Huixian ^a   Cargo, James ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; CHIP SCALE PACKAGES; COPPER; DEFECTS; DIELECTRIC MATERIALS; ELECTRIC RESISTANCE; FAILURE ANALYSIS; PHOTONS; REACTIVE ION ETCHING; RELIABILITY; SCANNING ELECTRON MICROSCOPY; VOLTAGE CONTROL;

CIRCUIT-UNDER-PAD (CUP); COPPER INTERCONNECTS; CROSS-SECTION ANALYSIS; INTERCONNECT RESISTANCE; PHOTON EMISSION MICROSCOPY (PEM);

INTEGRATED CIRCUITS;

EID: 14844310243     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Lawrence C. Wagner, "Failure analysis challenges", pp. 36-41, 2001 IPFA
2. Huixian Wu, James Cargo, Carl Peridier and Joe Serpiello, "Reliability issues and advanced failure analysis deprocessing techniques for copper/low k technology", pp. 536-544, 2003 IRPS
3. Huixian Wu and James Cargo, "Characterization of reactive ion etching of silicon substrate for backside failure mode analysis", ISTFA 2002
4. T. Sakura, H. Utsunumyia and et al., " A detailed study of soft- and pre-soft-breakdowns in small geometry MOS structures," pp. 183- 186, IEDM Tech. Dig., 1998
5. Huixian Wu, James Cargo, Barry Dutt and et al., "Interconnect and Gate Level Delayering Techniques for Cu/Low k Technology Failure Analysis", ISTFA 2003