Failure analysis challenges

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2001, Pages 36-41

  Wagner, L C ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENT MEASUREMENT; ELECTRON MICROSCOPY; FAILURE ANALYSIS; ITERATIVE METHODS; MICROELECTRONICS; OPTICAL MICROSCOPY; SOFTWARE ENGINEERING; TECHNOLOGICAL FORECASTING;

DEPROCESSING TECHNIQUES; ELECTRICAL CHARACTERIZATION; FAILURE SITE ISOLATION; LOCALIZATION PROCESS; PHYSICAL ANALYSIS; SYSTEMS-ON-A-CHIP;

INTEGRATED CIRCUIT TESTING;

EID: 0034832578     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Semiconductor industry association, international technology roadmap for semiconductors
2. Semiconductor product analysis challenges based on the 1999 ITRS
3. Failure analysis future requirements
4. ATE failure isolation methodologies for failure analysis, design debug and yield enhancement
5. Can failure analysis keep pace with IC technology development