Interconnect and Gate Level Delayering Techniques for Cu/Low k Technology Failure Analysis

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn 2003-November, Issue , 2003, Pages 90-98

  Wu, Huixian ^a   Cargo, James ^a   Dutt, Barry ^a   Bucha, Tony ^a   Serpiello, Joe ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; COPPER; INTEGRATED CIRCUIT INTERCONNECTS; LOW-K DIELECTRIC; RELIABILITY ANALYSIS;

COPPER LAYER; COPPER TECHNOLOGY; CU/LOW-K; DELAYERING; DIELECTRIC LAYER; GATE LEVELS; INTERCONNECT LEVELS; LOW-K INTER-LEVEL DIELECTRICS; PAPER FAILURES; TECHNOLOGY FAILURE;

FAILURE ANALYSIS;

EID: 14844306690     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.31399/asm.cp.istfa2003p0090     Document Type: Conference Paper

References (4)

1. Lawrence C. Wagner, "Failure analysis challenges", pp. 36-41, 2001 IPFA
2. Huixian Wu, James Cargo, Carl Peridier and Joe Serpiello, "Reliability issues and advanced failure analysis deprocessing techniques for copper/low k technology", pp. 536-544, 2003 IRPS
3. Huixian Wu and James Cargo, "Characterization of reactive ion etching of silicon substrate for backside failure mode analysis", ISTFA 2002
4. T. Sakura, H. Utsunumyia and et al., " A detailed study of soft- and pre-soft-breakdowns in small geometry MOS structures, " pp. 183- 186, IEDM Tech. Dig., 1998