The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction

ACM SIGPLAN Notices

Volumn 38, Issue 5, 2003, Pages 38-48

  Hsu, Chung Hsing ^a   Kremer, Ulrich ^a  

^a RUTGERS UNIVERSITY   (United States)

Author keywords

Dynamic voltage scaling; Energy savings

Indexed keywords

ALGORITHMS; COMPUTER SOFTWARE SELECTION AND EVALUATION; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY CONSERVATION; LAPTOP COMPUTERS; PROGRAM COMPILERS;

DYNAMIC VOLTAGE SCALING; ENERGY SAVINGS;

SOFTWARE ENGINEERING;

EID: 1442337874     PISSN: 03621340     EISSN: None     Source Type: Journal    
DOI: 10.1145/780822.781137     Document Type: Conference Paper

References (50)

1. N. AbouGhazaleh, D. Moosé, B. Childers, and R. Melhem. Toward the placement of power management points in real time applications. In Proceedings of the Workshop on Compilers and Operating Systems for Low Power, September 2001.
2. Advanced Micro Devices, Inc. Mobile AMD athlon 4 processor model 6 CPGA data sheet. Publication 24319, November 2001.
3. A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, A. Nicolau. Profile-based dynamic voltage scheduling using program checkpoints in the COPPER framework. In Proceedings of Design, Automation and Test in Europe Conference, March 2002.
4. D. Bailey. 21st century high-end computing. In Invited Talk, Applications, Algorithms, and Architectures Workshop for BlueGene/L, August 2002.
5. F. Bellosa. The benefits of event-driven energy accounting in power-sensitive systems. In Proceedings of 9th ACM SIGOPS European Workshop, September 2000.
6. S. Borkar. Design challenges of technology scaling. IEEE Micro, 19(4):23-29, July/August 1999.
7. D. Brooks, V. Tiwari, and M. Martonosi. Watch: A framework for achitectural-level power analysis and optimizations. In 27th International Symposium on Computer Architecture, June 2000.
8. T. Burd and R. Brodersen. Energy efficient CMOS microprocessor design. In the 28th Hawaii International Conference on System Sciences, January 1995.
9. D. Burger. Hardware Techniques to Improve the Performance of the Processor/Memory Interface. PhD thesis, Computer Sciences Department, University of Wisconsin-Madison, 1998.
10. L. Chandrasena and M. Liebelt. A rate selection algorithm for quantized undithered dynamic supply voltage scaling. In Proceedings of the International Symposium on Low-Power Electronics and Design, August 2000.
11. Transmeta Corporation. http://www.transmeta.com.
12. K. Flautner and T. Mudge. Vertigo: Automatic performance-setting for linux. In Proceedings of the 5th Symposium on Operating Systems Design and Implementation, December 2002.
13. K. Flautner, S. Reinhardt, and T. Mudge. Automatic performance-setting for dynamic voltage scaling. In Proceedings of the 7th Annual International Conference on Mobile Computing and Networking, July 2001.
14. R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 31(9):1277-1284, September 1996.
15. D. Grunwald, P. Levis, K. Farkas, C. Morrey III, and M. Neufeld. Policies for dynamic clock scheduling. In Proceedings of the 4th Symposium on Operating System Design and Implementation, October 2000.
16. C.-H. Hsu and U. Kremer. Dynamic voltage and frequency scaling for scientific applications. In Proceedings of the 14th annual workshop on Languages and Compilers for Parallel Computing, August 2001.
17. C.-H. Hsu and U. Kremer. Compiler-directed dynamic voltage scaling for memory-bound applications. Technical Report DCS-TR-498, Department of Computer Science, Rutgers University, August 2002.
18. C.-H. Hsu and U. Kremer. Single region vs. multiple regions: A comparison of different compiler-directed dynamic voltage scheduling approaches. In Workshop on Power-Aware Computer Systems, 2002.
19. C.-H. Hsu, U. Kremer, and M. Hsiao. Compiler-directed dynamic frequency and voltage scheduling. In Workshop on Power-Aware Computer Systems, November 2000.
20. C.-H. Hsu, U. Kremer, and M. Hsiao. Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors. In Proceedings of the International Symposium on Low-Power Electronics and Design, August 2001.
21. T. Ishihara and H. Yasuura. Voltage scheduling problem for dynamically variable voltage processors. In International Symposium on Low Power Electronics and Design, pages 197-202, August 1998.
22. S. Kim and A. Somani. Characterization of an extended multimedia benchmark on a general purpose microprocessor architecture. Technical Report DCNL-CA-2000-002, Electrical and Computer Engineering Department, Iowa State University, 2000.
23. K. Lahiri, A. Raghunathan, S. Dey, and D. Panigrahi. Battery-driven system design: A new frontier in low power design. In Asia South Pacific Design Automation Conference / International Conference on VLSI Design, January 2002.
24. B. Lee and L. John. Implications of programmable general purpose processors for compression/encryption applications. In IEEE 13th International Conference on Application-specific Systems, Architectures and Processors, July 2002.
25. S. Lee and T. Sakurai. Run-time voltage hopping for low-power real-time systems. In Proceedings of the 37th Conference on Design Automation, pages 806-809, June 2000.
26. J. Lorch and A. Smith. Improving dynamic voltage algorithms with PACE. In Proceedings of the International Conference on Measurement and Modeling of Computer Systems, June 2001.
27. Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron. Control-theoretic dynamic frequency and voltage scaling for multimedia workloads. In Proceedings of the 2002 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, October 2002.
28. D. Marculescu. On the use of microarchitecture-driven dynamic voltage scaling. In Workshop on Complexity-Effective Design, June 2000.
29. T. Martin and D. Siewiorek. Nonideal battery and main memory effects on cpu speed setting for low power. IEEE Transactions on Very Large Scale Integration System, 9(1):29-34, February 2001.
30. T. L. Martin. Balancing Batteries, Power, and Performance: System Issues in CPU Speed-Setting for Mobile Computing. PhD thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennyslvania, 1999.
31. K. Masahiro, K. Kazuo, H. Kazuo, and O. Eiichi. WT110/WT130 digital power meters. Yokogawa Technical Report 22, 1996.
32. A. Miyoshi, C. Lefurgy, E. Hensbergen, and R. Rajkumar. Critical power slope: Understanding the runtime effects of frequency scaling. In Proceedings of the 16th Annual ACM International Conference on Supercomputing, June 2002.
33. D. Mossé, H. Aydin, B. Childers, and R. Melhem. Compiler-assisted dynamic power-aware scheduling for real-time applications. In Workshop on Compiler and Operating Systems for Low Power, October 2000.
34. T. Mudge. Power: A first class design constraint for future architectures. IEEE Computer, 34(4):52-58, April 2001.
35. M. Pedram and Q. Wu. Design considerations for battery-powered electronics. In Proceedings of the 36th Conference on Design Automation, June 1999.
36. T. Pering, T. Burd, and R. Brodersen. The simulation and evaluation of dynamic voltage scaling algorithms. In Proceedings of 1998 International Symposium on Low Power Electronics and Design, pages 76-81, August 1998.
37. P. Pillai and K. Shin. Real-time dynamic voltage scaling for low-power embedded operating systems. In Proceedings of the 18th Symposium on Operating Systems Principles, October 2001.
38. R. Rajamony and R. Bianchini. Energy management for server clusters. In Tutorial, 16th Annual ACM International Conference on Supercomputing, June 2002.
39. H. Saputra, M. Kandemir, N. Vijaykrishnan, M.J. Irwin, J. Hu, C.-H. Hsu, and U. Kremer. Energy-conscious compilation based on voltage scaling. In ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems and Software and Compilers for Embedded Systems, June 2002.
40. D. Shin and J. Kim. A profile-based energy-efficient intra-task voltage scheduling algorithm for hard real-time applications. In Proceedings of the International Symposium on Low-Power Electronics and Design, August 2001.
41. T. Simunic, L. Benini, A. Acquaviva, P. Glynn, and G. De Micheli. Dynamic voltage scaling for portable systems. In Proceedings of the 38th Design Automation Conference, June 2001.
42. A. Sinha and A. Chandrakasan. Dynamic voltage scheduling using adaptive filtering of workload traces. In Proceedings of the 14th International Conference on VLSI Design, January 2001.
43. N. Slingerland and A. Smith. Cache performance for multimedia applications. In Proceedings of the 15th IEEE International Conference on Supercomputing, June 2001.
44. S. Sohoni, Z. Xu, R. Min, and Y. Hu. A study of memory system performance of multimedia applications. In ACM Joint International Conference on Measurement & Modeling of Computer Systems, June 2001.
45. SUIF. Stanford University Intermediate Format.
46. RLX Technologies. Serverblade. http://www.rlxtechnologies.com.
47. K. van den Doel, P. Kry, and D. Pai. Foley Automatic: Physically-based sound effects for interactive simulation and animation. In Proceedings of the 28th annual conference on Computer graphics and interactive techniques, August 2001.
48. F. Xie and M. Martonosi and S. Malik. Compile time dynamic voltage scaling settings: Opportunities and limits. In Proceedings of the ACM SIGPLAN Conference on Programming Languages Design and Implementation, June 2003.
49. F. Yao, A. Demers, and S. Shenker. A scheduling model for reduced cpu energy. In IEEE Annual Symposium on Foundations of Computer Science, pages 374-382, October 1995.
50. W. Ye, N. Vijaykrishna, M. Kandemir, and M.J. Irwin. The design and use of SimplePower: A cycle-accurate energy estimation tool. In Design Automation Conference, June 2000.