40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 11, 2003, Pages 1830-1837

  Kehrer, Daniel ^a   Wohlmuth, Hans Dieter ^a   Knapp, Herbert ^a   Wurzer, Martin ^a   Scholtz, Arpad L ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

CMOS; Current mode logic; Demultiplexer; Inductive peaking; Multiplexer

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC INDUCTORS; EQUIVALENT CIRCUITS; FLIP FLOP CIRCUITS; INDUCTANCE; INTEGRATED CIRCUIT MANUFACTURE; MATHEMATICAL MODELS; MOSFET DEVICES; MULTIPLEXING EQUIPMENT;

CURRENT MODE LOGIC; DEMULTIPLEXER; MASTER-SLAVE FLIP-FLOP; MASTER-SLAVE-MASTER FLIP FLOP; MULTIPLEXER;

CMOS INTEGRATED CIRCUITS;

EID: 0242468193     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.818297     Document Type: Article

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