Clock period minimization of semi-synchronous circuits by gate-level delay insertion

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E82-A, Issue 11, 1999, Pages 2383-2389

  Yoda, Tomoyuki ^a   Takahashl, Atsushi ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Clock period minimization; Delay insertion; Semisynchronous circuit

Indexed keywords

EID: 13444260318     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (7)

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5. A. Takahashi K. Inoue and Y. Kajitani Clock-tree routing realizing a clock-schedule for semi-synchronous circuits Proc. 1997 ICCAD pp.260-265 1997.
6. [G] A. Takahashi and Y. Kajitani Performance and reliability driven clock scheduling of sequential logic circuits Proc. ASP-DAG ' 97 pp.37-42 1997.
7. A. Takahashi W. Takahashi and Y. Kajitani Clockrouting driven layout methodology for semi-synchronous circuit design Proc. TAU' 97 pp.63-66 1997.