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IEEE Electron Device Letters

Volumn 25, Issue 2, 2004, Pages 104-106

AC Behavior of Gate-Induced Floating Body Effects in Ultrathin Oxide PD SOI MOSFETs

(3) Lederer, Dimitri a Flandre, Denis a Raskin, Jean Pierre a

a UNIVERSITÉ CATHOLIQUE DE LOUVAIN (Belgium)

Author keywords

AC analysis; Floating body effects; Gate tunneling; Partially depleted (PD) silicon on insulator (SOI) MOSFETs

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; IONIZATION; MATHEMATICAL MODELS; MICROELECTRONICS; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; TRANSCONDUCTANCE;

FLOATING BODY EFFECTS; GATE TUNNELING;

MOSFET DEVICES;

EID: 1342265608 PISSN: 07413106 EISSN: None Source Type: Journal
DOI: 10.1109/LED.2003.822658 Document Type: Article

Times cited : (13)

References (8)

1
- 84948456795
- Studying the impact of the gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD
- San Jose, CA
- P. Su, S. K. H. Fung, W. Liu, and C. Hu, "Studying the impact of the gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD," in Proc. Int. Symp. on Quality Electronic Design, San Jose, CA, 2002, pp. 75-76.
- (2002) Proc. Int. Symp. on Quality Electronic Design , pp. 75-76
- Su, P.¹ Fung, S.K.H.² Liu, W.³ Hu, C.⁴

2
- 0034795708
- Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM
- Kyoto, Japan
- R. V. Joshi, C. T. Chuang, S. K. H. Fung, F. Assaderaghi, M. Sherony, I. Yang, and G. Shahidi, "Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM," in VLSI Tech. Dig., Kyoto, Japan, 2001, pp. 75-76.
- (2001) VLSI Tech. Dig. , pp. 75-76
- Joshi, R.V.¹ Chuang, C.T.² Fung, S.K.H.³ Assaderaghi, F.⁴ Sherony, M.⁵ Yang, I.⁶ Shahidi, G.⁷

3
- 84907704789
- New mechanism of body charging in partially depleted SOI MOSFETs with ultrathin gate oxides
- Florence, Italy
- J. Pretet, T. Matsumoto, S. Cristoloveanu, R. Gwoziecki, C. Raynaud, A. Roveda, and H. Brut, "New mechanism of body charging in partially depleted SOI MOSFETs with ultrathin gate oxides," in Proc. ESSDERC, Florence, Italy, 2002, pp. 515-518.
- (2002) Proc. ESSDERC , pp. 515-518
- Pretet, J.¹ Matsumoto, T.² Cristoloveanu, S.³ Gwoziecki, R.⁴ Raynaud, C.⁵ Roveda, A.⁶ Brut, H.⁷

4
- 0041441251
- Linear kink effect induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETs
- July
- A. Mercha, J. M. Rafi, E. Simoen, E. Augendre, and C. Claeys, "Linear kink effect induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETs," IEEE Trans. Electron Devices, vol. 50, pp. 1675-1682, July 2003.
- (2003) IEEE Trans. Electron Devices , vol.50 , pp. 1675-1682
- Mercha, A.¹ Rafi, J.M.² Simoen, E.³ Augendre, E.⁴ Claeys, C.⁵

5
- 0026904737
- A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFETs
- Oct.
- R. Howes and W. Redman-White, "A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFETs," IEEE J. Solid-State Circuits, vol. 27, pp. 1186-1192, Oct. 1992.
- (1992) IEEE J. Solid-state Circuits , vol.27 , pp. 1186-1192
- Howes, R.¹ Redman-White, W.²

6
- 0003750001
- New York: McGraw-Hill
- Y. P. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1987.
- (1987) Operation and Modeling of the MOS Transistor
- Tsividis, Y.P.¹

7
- 0036637862
- SOI n-MOSFET low-frequency noise measurements and modeling from room temperature up to 250°C
- Nov.
- V. Dessard, B. Iniguez, S. Adriaensen, and D. Flandre, "SOI n-MOSFET low-frequency noise measurements and modeling from room temperature up to 250°C." IEEE Trans. Electron Devices, vol. 49, pp. 1289-1295, Nov. 2002.
- (2002) IEEE Trans. Electron Devices , vol.49 , pp. 1289-1295
- Dessard, V.¹ Iniguez, B.² Adriaensen, S.³ Flandre, D.⁴

8
- 20244379465
- [Online]
- [Online], Available: www-device.eecs.berkeley.edu/̃bsimsoi

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.