Fatal void size comparisons in via-below and via-above Cu dual-damascene interconnects

Materials Research Society Symposium Proceedings

Volumn 812, Issue , 2004, Pages 373-378

  Choi, Z S ^a   Gan, C L ^b,c   Wei, F ^a   Thompson, C V ^a,b   Lee, J H ^d   Pey, K L ^b   Choi, W K ^b  

^a Massachusetts Institute of Technology Cambridge   (United States)

^b SINGAPORE MIT ALLIANCE   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^d Department of Electrical Engineering and Computer Science   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CATHODES; COMPUTER SIMULATION; COPPER; CURRENT DENSITY; ELECTROMIGRATION; FAILURE ANALYSIS; ION BEAMS; MATHEMATICAL MODELS; NUCLEATION; SCANNING ELECTRON MICROSCOPY; TENSILE STRESS;

FAILURE MECHANISMS; SHORTEST-TIMES-TO-FAILURE (STTF); VOID GROWTH; VOID SIZE;

INTERCONNECTION NETWORKS;

EID: 12844284528     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1557/proc-812-f7.6     Document Type: Conference Paper

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