Planarization issues in wafer-level three-dimensional (3D) integration

Materials Research Society Symposium Proceedings

Volumn 816, Issue , 2004, Pages 217-228

  Lu, J Q ^a   Rajagopalan, G ^a   Gupta, M ^a   Cale, T S ^a   Gutmann, R J ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADHESIVES; BONDING; DIELECTRIC MATERIALS; ELECTRONICS PACKAGING; POLISHING; SILICON ON INSULATOR TECHNOLOGY; THIN FILM TRANSISTORS; THREE DIMENSIONAL;

COPPER DAMASCENE PATTERNING; HIGH DENSITY MULTIFUNCTIONAL INTEGRATION (HDMI); THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS; WAFER BONDING;

WSI CIRCUITS;

EID: 12744260669     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1557/proc-816-k7.7     Document Type: Conference Paper

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