Equalization and near-end crosstalk (NEXT) noise cancellation for 20-Gb/s 4-PAM backplane serial I/O interconnections

IEEE Transactions on Microwave Theory and Techniques

Volumn 53, Issue 1, 2005, Pages 246-254

  Hur, Youngsik ^a   Maeng, Moonkyun ^a   Chun, Carl ^a   Bien, Franklin ^a,b   Kim, Hyoungsoo ^a   Chandramouli, Soumya ^a   Gebara, Edward ^b,c   Laskar, Joy ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Quellan Inc   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

0.18 m CMOS; 20 Gb s; Backplane; Equalization; Finite impulse response (FIR) filter; Four level pulse amplitude modulation (4 PAM); Input output (I O) interconnection; LC ladder; Near end crosstalk (NEXT) noise cancellation; Tunable pole zero (PZ) filter

Indexed keywords

AMPLITUDE MODULATION; CMOS INTEGRATED CIRCUITS; CROSSTALK; DATA COMMUNICATION SYSTEMS; EQUALIZERS; FIR FILTERS; INPUT OUTPUT PROGRAMS; SPURIOUS SIGNAL NOISE;

0.18-ΜM CMOS; 20 GB/S; BACKPLANE; EQUALIZATION; FOUR-LEVEL PULSE AMPLITUDE MODULATION (4-PAM); INPUT/OUTPUT (I/O) INTERCONNECTION; LC LADDER; NEAR-END CROSSTALK (NEXT) NOISE CANCELLATION; TUNABLE POLE-ZERO (PZ) FILTERS;

INTERCONNECTION NETWORKS;

EID: 12344286339     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2004.839311     Document Type: Conference Paper

References (14)

1. J. T. Stonick, G. Wei, J. L. Sonntag, and D. K. Weinlader, "An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 436-443, Mar. 2003.
2. M. Maeng, F. Bien. Y. Hur, S. Chandramouli, H. Kim, Y. Kumar, C. Chun, E. Gebara, and J. Laskar, "A 0.18 μm CMOS equalizer with an improved multiplier for 4-PAM/20 Gbps throughput over 20-in FR-4 backplane channels," in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2004, pp. 105-108.
3. Y. Hur, M. Maeng, S. Chandramouli, F. Bien, E. Gebara, K. Lim, and J. Laskar, "4-PAM 20 Gbs transmission over 20-in FR-4 backplane channels: Channel characterization and system implementation," presented at the IMAPS Advanced Technology High-Speed Interconnect, EMC and Power Workshop, Oct. 2003.
4. D. Mijuskovic, "Backplane communication: 5 Gb/sec and beyond," presented at the Smart Network Developer Forum, Mar. 2003.
5. F. Bien, A. Kim, M. Vrazel, E. Gebara, S. Bajekal, A. Ragvahan, Z. Nami, C. Lee, B. Schmukler, and J. Laskar, "A 0.18 μm CMOS fully integrated 6.25 Gbps single aggressor multi-rate crosstalk cancellation IC for legacy backplane and interconnect applications," presented at the IEEE Signal Propagation on Interconnects Workshop, May 2004.
6. J. Ortega and A. Elco, "Shielded differential connector delivers increased bandwidth and signal integrity performance," in Proc. 49th Electronic Components and Technology Conf., Jun. 1999, pp. 525-529.
7. J. Nickel, J. Rosenberger, S. W. Crane, Jr., C. Ogata, J. Jeon, P. T. Codd, Z. Horvath, and A. C. Cangellaris, "Optimized interconnect solution for high-performance system data transmission," presented at the IMAPS Advanced Technology High-Speed Interconnect, EMC and Power Workshop, Oct. 2003.
8. J. L. Zerbe, P. S. Chau, C. W. Werner, W. F. Stonecypher, H. J. Liaw, G. J. Yeh, T. P. Thrush, S. C. Best, and K. S. Donnelly, "A 2 Gb/s/pin 4-PAM parallel bus interface with crosstalk cancellation, equalization, and integrating receivers," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2001, pp. 66-67.
9. J. L. Zerbe, C. W. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W. F. Stonecypher, A. Ho, T. P. Thrush, R. T. Kollipara, M. A. Horowitz, and K. S. Donnelly, "Equalization and clock recovery for a 2.5-10 Gb/s 2-PAM/4-PAM backplane transceiver cell," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2121-2130, Dec. 2003.
10. A. J. Kim, M. Vrazel, V. M. Hietala, E. Gebara, C. Pelardl, S. Bajekal, S. E. Ralph, and J. Laskar, "Equalization and the evolution of Gb communications," in IEEE GaAs Integrated Circuits Symp. Tech. Dig., Nov. 2003, pp. 193-196.
11. F. Krummenacher and N. Joehl, "A 4 MHz CMOS continuous-time filter with on-chip automatic tuning," IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 750-758, Jun. 1988.
12. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 2003.
13. F. Yuan, "Fully differential 8-to-l current-mode multiplexer for 10 Gbit/s serial links in 0.18 μm CMOS," Electron. Lett., vol. 40, no. 13, pp. 789-790, Jun. 2004.
14. V. Vrodanov and M. Green, "A differential active load and its applications in CMOS analog circuit designs," IEEE Trans. Circuit Syst. II, Analog Digit. Signal Process., vol. 44. no. 4, pp. 265-273, Apr. 1997.