A 0.18μm CMOS fully integrated 6.25Gbps single aggressor multi-rate crosstalk cancellation IC for legacy backplane and interconnect applications

Proceedings - 8th IEEE Workshop on Signal Propagation on Interconnects

Volumn , Issue , 2004, Pages 73-76

  Bien, F ^a,b   Raghavan, A ^a   Nami, Z ^a   Lee, C H ^a,b   Kim, A ^a   Vrazel, M ^a   Gebara, E ^a,b   Bajekal, S ^a   Schmukler, B ^a   Laskar, J ^a,b  

^a Quellan Inc   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA RATE; INTERCONNECTS; NEAR END CROSS TALK (NEXT); SIGNAL FIDELITY;

BIT ERROR RATE; CROSSTALK; DATA REDUCTION; DIELECTRIC LOSSES; ELECTRIC CONNECTORS; NATURAL FREQUENCIES; SIGNAL RECEIVERS; SPECTRUM ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 10044267803     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A. J. Kim et. al., "Equalization and the Evolution of Gigabit Communications", GaAs IC 2003, pp. 193-196.
2. Hui Wu, et. al, " Integrated transversal equalizers in high-speed fiber-optic systems", IEEE J. Solid-State Circuits, vol. 38, pp 2131-2137, Dec 2003.
3. H. Liaw, et. al., "A 1.6 Gbit/s/pin Multilevel Parallel Interconnection," DesignCon 2001.
4. Y. Hur, et. al., "4-PAM/20Gbps Transmission over 20-in FR-4 Backplane Channels: Channel Characterization and System Implementation", IMAPS
5. M. Maeng, et. Al, "A 0.18um-CMOS Equalizer with an Improved Multiplier for 4-PAM/20Gbps Throughput Over 20-inch FR-4 Backplane Channels," (accepted) IEEE IMS-2004 MTT Conference
6. B. Razavi, "Design of Analog CMOS Integrated Circuits", pp458-463, McGraw-Hill, 2001