Hardware-software co-synthesis of hard real-time systems with reconfigurable FPGAs

Computers and Electrical Engineering

Volumn 30, Issue 7, 2004, Pages 471-489

  Ali, Faridah M ^a   Das, A Shoba ^a  

^a KUWAIT UNIVERSITY   (Kuwait)

Author keywords

Hard real time; Hardware software co synthesis; Precedence constraint; Reconfigurable FPGA

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER SOFTWARE; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; GRAPH THEORY; HEURISTIC PROGRAMMING; INTEGER PROGRAMMING; INTEGRATED CIRCUITS; PROBLEM SOLVING; SCHEDULING;

HARD REAL-TIME; HARDWARE-SOFTWARE CO-SYNTHESIS; PRECEDENCE CONSTRAINT; RECONFIGURABLE FPGA;

REAL TIME SYSTEMS;

EID: 12344274519     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.compeleceng.2004.09.001     Document Type: Article

References (19)

1. F. Slomka, M. Dorfel, R. Munzenberger, and R. Hofmann Hardware/software codesign and rapid prototyping of embedded systems IEEE Des. Test Comput. April-June 2000 28 38
2. R. Ernst Codesign of embedded systems: status and trends IEEE Des. Test Comput. April-June 1998 45 54
3. Dave BP, Jha. CASPER: Concurrent hardware-software co-synthesis of hard real-time aperiodic and periodic specification of embedded system architecture. In: Proceedings of design, automation and test in Europe, IEEE Computer Society, 1998, p. 118-24
4. Niemann R, Marwedel P. Hardware/software partitioning using integer programming. In: Proceedings of European Design and Test Conference 1996, p. 473-9
5. Lin T, Sait S, Cybre W. Buffer size driven partitioning for HW/SW co-design, ICCD'98, p. 569-601
6. Hou J, Wolf W. Process partitioning for distributed embedded systems. In: International Workshop on Hardware/Software Co-design, 1996, p. 70-6
7. H. Liu, and D.F. Wong Integrated partitioning and scheduling for hardware/software co-design Proc. Int. Conf. Comput. Des. 1998 609 614
8. Axelsson J. Analysis and improvement of task schedulability in hardware/software codesign. In: Proceedings of 7 EUROMICRO Workshop on Real-Time Systems, 1995, p. 276-83
9. Shin Y, Chio K. Enforcing schedulability of multi-task systems by hardware-software codesign. In: International Workshop on Hardware/Software Co-Design, 1997, p. 3-7
10. G.C. Buttazz Hard real-time computing systems-predictable scheduling algorithms 1997 Kluwer Academic Publishers
11. Jeong B, Yoo S, Lee S, Choi K. Hardware-software co-synthesis for run-time incrementally reconfigurable FPGAs. In: Proceedings of Asia & South Pacific Design Automation, Jan. 2000, p. 169-74
12. B. Michael A reconfigurable computing primer Multimedia Syst. Des. September 1998 44 47
13. Dick RP, Jha NK. CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems. In: Proceedings of International Conference on Computer-Aided Design, November 1998, p. 62-8
14. Standard Task Graph Set Archive, http://www.Kasahara.elec.waseda.jp/schedule
15. M.R. Garey, and D.S. Johnson Computers and Intractability: A guide to the Theory of NP-Completeness 1979 W.H. Freeman and Company
16. K. Chatha, and R. Vemuri An interactive algorithm for hardware-software partitioning, hardware design space exploration and scheduling Des. Automata Embedded Syst. 5 2000 282 293
17. C.M. Krishna, and K.G. Shin Real-Time Systems 1997 McGraw-Hill
18. Dave BP. CRUSADE: Hardware/software co-synthesis of dynamically reconfigurable heterogeneous real-time distributed embedded systems. In: Proceedings of design, Automation & Test in Europe Conference, March 1999, p. 97-104
19. Noguera J, Badia R. A HW/SW partitioning algorithm for dynamically reconfigurable architectures. In: Proceedings of Design, Automation and Test in Europe Conference, March 2001, p. 729-34