Buffer size driven partitioning for HW/SW co-design

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1998, Pages 596-601

  Lin, Ta Cheng ^a   Sait, Sadiq M ^a   Cyre, Walling R ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUFFER STORAGE; COMPUTER HARDWARE; COMPUTER SOFTWARE; CONSTRAINT THEORY; DATA COMMUNICATION SYSTEMS; DATA TRANSFER; FIELD PROGRAMMABLE GATE ARRAYS; GENETIC ALGORITHMS; MICROPROCESSOR CHIPS; OPTIMIZATION; SIMULATED ANNEALING;

LIST SCHEDULING; PARTITIONING; SYSTEM DELAY;

DATA FLOW ANALYSIS;

EID: 0032301247     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)