-
1
-
-
0000076482
-
Set partitioning: A survey
-
E. Balas and M. Padberg. Set partitioning: A survey. SIAM Review, (18):710-760, 1976.
-
(1976)
SIAM Review
, Issue.18
, pp. 710-760
-
-
Balas, E.1
Padberg, M.2
-
2
-
-
0034852693
-
From architecture to layout: Partitioned memory synthesis for embedded systems-on-chip
-
L. Benini, L. Macchiarulo, A. Macii, E. Macii, and M. Poncino. From architecture to layout: Partitioned memory synthesis for embedded systems-on-chip. In Proc. of DAC, pages 784-789, 2001.
-
(2001)
Proc. of DAC
, pp. 784-789
-
-
Benini, L.1
Macchiarulo, L.2
Macii, A.3
Macii, E.4
Poncino, M.5
-
3
-
-
0342518162
-
Lp_solve: A mixed integer linear program solver
-
Eindhoven University of Technology
-
M. Berkelaar. lp_solve: A Mixed Integer Linear Program Solver. Technical report, Eindhoven University of Technology.
-
Technical Report
-
-
Berkelaar, M.1
-
4
-
-
0001868375
-
Global communication and memory optimizing transformations for low power signal processing systems
-
F. Catthoor et al. Global communication and memory optimizing transformations for low power signal processing systems. In Proc. of Int. Workshop on Low Power Design, pages 51-56, 1994.
-
(1994)
Proc. of Int. Workshop on Low Power Design
, pp. 51-56
-
-
Catthoor, F.1
-
6
-
-
0025554392
-
The combination of scheduling, allocation and mapping in a single algorithm
-
R. Cloutier and D. Thomas. The combination of scheduling, allocation and mapping in a single algorithm. In Proc. of DAC, pages 71-76, 1990.
-
(1990)
Proc. of DAC
, pp. 71-76
-
-
Cloutier, R.1
Thomas, D.2
-
7
-
-
0025385726
-
Architecture driven synthesis techniques for mapping digital signal processing structures into silicon
-
Feb.
-
H. De Man et al. Architecture driven synthesis techniques for mapping digital signal processing structures into silicon. Proc. of IEEE, 78(2):319-335, Feb. 1990.
-
(1990)
Proc. of IEEE
, vol.78
, Issue.2
, pp. 319-335
-
-
De Man, H.1
-
12
-
-
84861281335
-
-
IMEC. ATOMIUM Project, http://www.imec.be/atomium.
-
ATOMIUM Project
-
-
-
13
-
-
1242286076
-
A compiler-based approach for dynamically managing scratch-pad memories in embedded systems
-
Feb.
-
M. Kandemir et al. A compiler-based approach for dynamically managing scratch-pad memories in embedded systems. IEEE TCAD, 23(2):243-260, Feb. 2004.
-
(2004)
IEEE TCAD
, vol.23
, Issue.2
, pp. 243-260
-
-
Kandemir, M.1
-
14
-
-
0348129864
-
The MIMOLA system: Detailed description of the system software
-
P. Marwedel. The MIMOLA system: Detailed description of the system software. In Proc. of DAC, pages 59-63, 1993.
-
(1993)
Proc. of DAC
, pp. 59-63
-
-
Marwedel, P.1
-
15
-
-
0030781358
-
Behavioral array mapping into multiport memories targetting low power
-
Jan.
-
P. Panda and N. Dutt. Behavioral array mapping into multiport memories targetting low power. In Proc. of Int. Conf. VLSI Design, pages 268-272, Jan. 1997.
-
(1997)
Proc. of Int. Conf. VLSI Design
, pp. 268-272
-
-
Panda, P.1
Dutt, N.2
-
17
-
-
0028076680
-
An algorithm for array variable clustering
-
Mar.
-
L. Ramachandran, D. Gajski, and V. Chaiyakul. An algorithm for array variable clustering. In Proc. of DAC, pages 262-266, Mar. 1994.
-
(1994)
Proc. of DAC
, pp. 262-266
-
-
Ramachandran, L.1
Gajski, D.2
Chaiyakul, V.3
-
18
-
-
0009755242
-
Iterative modulo scheduling: An algorithm for software pipelining loops
-
Dec.
-
B. Rau. Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops. In Proc of Micro-27, Dec. 1994.
-
(1994)
Proc of Micro-27
-
-
Rau, B.1
-
21
-
-
0036603298
-
PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators
-
Jun.
-
R. Schreiber et al. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 31(2):127-142, Jun. 2002.
-
(2002)
Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
, vol.31
, Issue.2
, pp. 127-142
-
-
Schreiber, R.1
-
23
-
-
0035704608
-
Synthesis of hardware models in C with pointers and compelx data structures
-
Dec.
-
L. Semeria, K. Sato, and G. De Micheli. Synthesis of hardware models in C with pointers and compelx data structures. IEEE Transactions on VLSI Systems, 9(6):743-756, Dec. 2001.
-
(2001)
IEEE Transactions on VLSI Systems
, vol.9
, Issue.6
, pp. 743-756
-
-
Semeria, L.1
Sato, K.2
De Micheli, G.3
-
24
-
-
0036047095
-
An integrated algorithm for memory allocation and assignment in high-level synthesis
-
J. Seo, T. Kim, and P. Panda. An integrated algorithm for memory allocation and assignment in high-level synthesis. In Proc. of 39th conference on Design Automation, pages 609-611, 2002.
-
(2002)
Proc. of 39th Conference on Design Automation
, pp. 609-611
-
-
Seo, J.1
Kim, T.2
Panda, P.3
-
28
-
-
0028581612
-
Memory estimation in high-level synthesis
-
June
-
I. Verbauwhede, C. Scheers, and J. Rabaey. Memory estimation in high-level synthesis. In Proc. of DAC, pages 143-148, June 1994.
-
(1994)
Proc. of DAC
, pp. 143-148
-
-
Verbauwhede, I.1
Scheers, C.2
Rabaey, J.3
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