From architecture to layout: Partitioned memory synthesis for embedded systems-on-chip

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 784-789

  Benini, L ^a   Macchiarulo, L ^b   Macii, A ^b   Macii, E ^b   Poncino, M ^b  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; OPTIMIZATION; STATIC RANDOM ACCESS STORAGE;

PARTIONED MEMORY SYNTHESIS;

EMBEDDED SYSTEMS;

EID: 0034852693     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2001.156243     Document Type: Article

References (16)

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