High-level synthesis of distributed logic-memory architectures

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 564-571

  Huang, Chao ^a   Ravi, Srivaths ^b   Raghunathan, Anand ^b   Jha, Niraj K ^a  

^a Princeton University   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED LOGIC-MEMORY ARCHITECTURE; HIGH-LEVEL SYNTHESIS; REGISTER TRANSFER LEVEL;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; DISTRIBUTED COMPUTER SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT TESTING; MATRIX ALGEBRA; RANDOM ACCESS STORAGE;

LOGIC DESIGN;

EID: 0036907086     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774655     Document Type: Conference Paper

References (37)

1. D. D. Gajski, N. D. Dutt, A. C-H Wu, and S. Y-L Lin, High-level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, Norwell, MA, 1992.
2. G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York, NY, 1994.
3. I. M. Verbhauwehede, C. J. Scheers, and J. Rabaey, "Memory estimation in high-level synthesis," in Proc. Design Automation Conf., June 1994, pp. 143-148.
4. Y. Zhao and S. Malik, "Exact memory size estimation for array computations," IEEE Trans. VLSI Systems, vol. 8, no. 5, pp. 517-521, Oct. 2000.
5. F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. De Man, "Global communication and memory optimizing transformations for low power signal processing systems," in Proc. Int. Wkshp. Low Power Design, 1994, pp. 51-56.
6. P. Marwedel, "The MIMOLA system: Detailed description of the system software," in Proc. Design Automation Conf., June 1993, pp. 59-63.
7. H. De Man, F. Catthoor, G. Goossens, J. V. Meerbergen, J. rabaey, and J. Huisken, "Architecture driven synthesis techniques for mapping digital signal processing structures into silicon," Proc. IEEE, vol. 78, no. 2, pp. 319-335, Feb. 1990.
8. R. Cloutier and D. Thomas, "The combination of scheduling, allocation, and mapping in a single algorithm," in Proc. Int. Symp. Microarchitecture, Dec. 1996, pp. 126-137.
9. N. Dutt, P. R. Panda, and A. Nicolau, Memory Issues in Embedded Systems-on-chip: Optimizations and Exploration, Kluwer Academic Publishers, Norwell, MA, 1998.
10. D. Thomas, Algorithmic and Register-transfer Level Synthesis: The System Architect's Workbench, Kluwer Academic Publishers, Norwell MA, 1990.
11. L. Ramachandran, D.D. Gajski, and V. Chaiyakul, "An algorithm for array variable clustering," in Proc. European Design Automation Conf., Mar. 1994, pp. 262-266.
12. H. Schmidt, "Synthesis of application-specific memory designs," IEEE Trans. VLSI Systems, vol. 5, no. 1, pp. 101-111, Mar. 1997.
13. P. R. Panda and N. D. Dutt, "Behavioral array mapping into multiport memories targeting low power," in Proc. Int. Conf. VLSI Design, Jan. 1997, pp. 268-272.
14. P. K. Jha and N. D. Dutt, "High-level library mapping for memories," ACM Trans. Design Automation of Electronic Systems, no. 3, pp. 566-603, July 2000.
15. O. Sentieys, D. Chillet, J. P. Diguet, and J. L. Phillipe, "Memory module selection for high-level synthesis," in Proc. VLSI Signal Processing IX, Oct. 1996, pp. 273-282.
16. N. D. Holmes and D. D. Gajski, "Architecture exploration for datapaths with memory hierarchy," in Proc. European Design & Test Conf., Mar. 1995, pp. 340-344.
17. F. Balasa, Background Memory Allocation for Multi-dimensional Signal Processing, Ph.D. thesis, ESAT/EE Dept., K.U.Leuven, Belgium, 1995.
18. K. S. Khouri, G. Lakshminarayana, and N. K. Jha, "Memory binding for performance optimization of control-flow intensive behaviors," in Proc. Int. Conf. Computer-Aided Design, Nov. 1999, pp. 482-488.
19. J. L. da Silva, F. Catthoor, D. Verkest, and H. De Man, "Power exploration for dynamic data types through virtual memory management refinement," in Proc. Int. Symp. Low Power Electronics & Design, Aug. 1998.
20. L. Semeria, K. Sato, G. De Micheli, "Synthesis of hardware models in C with pointers and complex data structures," IEEE Trans. VLSI Systems, vol. 9, no. 6, pp. 743-756, Dec. 2001.
21. F. Catthoor, S. Wuytack, E. De Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle, Custom Memory Management Methodology, Kluwer Academic Publishers, Norwell, MA, 1998.
22. ATOMIUM Project, IMEC, http://www.imec.be/atomium
23. F. Vahid, "Techniques for minimizing and balancing I/O during functional partitioning," IEEE Trans. Computer-Aided Design, vol. 18, no. 1, pp. 69-75, Jan. 1999.
24. C. E. Kozyrakis, S. Perissakis, D. Patterson, T. Anderson, K. Asanovic̀, N. Cardwell, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, R. Thomas, N. Treuhaft, and K. Yelick, "Scalable processors in the billion-transistor era: IRAM," Computer, vol. 30, no. 9, pp. 75-78, Sept. 1997.
25. M. Oskin, F. T. Chong, and T. Sherwood, "Active pages: A computation model for intelligent memory," in Proc. Int. Symp. Computer Architecture, June 1998, 192-203
26. Y. Kang, M. Huang, S. Yoo, Z. Ge, D. Keen, V. Lam, P. Pattnaik, and J. Torrellas, "Flexram: Toward an advanced intelligent memory system," Oct. 1999.
27. K. Mai, T. Paaske, N. Jayasena, R. Ho, W. J. Dally, and M. Horowitz, "Smart memories: A modular reconfigurable architecture," in Proc. Int. Symp. Computer Architecture, June 2000, pp. 161-171.
28. A. Agarwal, D. A. Kranz, and V. Natarajan, "Automatic partitioning of parallel loops and data arrays for distributed shared-memory multiprocessors," IEEE Trans. Parallel & Distributed Systems, vol. 6, no. 9, pp. 943-962, Sept. 1995.
29. J.-A. M. Anderson, "Automatic computation and data decomposition for multiprocessors," Tech. Rep. CSL-TR-97-719, Computer Systems Lab, EECS, Stanford Univ., Standford, CA, Mar. 1997.
30. A. W. Lim, Improving Parallelism and Data Locality with Affine Partitioning, Ph.D. thesis, Department of Computer Science, Stanford University, Stanford, CA, Aug. 2001.
31. J. Ramanujam and P. Sadayappan, "Tiling multidimensional iteration spaces for multicomputers," J. Parallel & Distributed Computing, vol. 16, no. 2, pp. 108-230, 1992.
32. M. de Berg, M. van Kreveld, M. Overmars, and O. Schwarzkopf, Computational Geometry, Springer-Verlag, 1997.
33. R. Potasman, J. Lis, A. Nicolau, and D. Gajski, "Percolation based synthesis," in Proc. Design Automation Conf., June 1990, pp. 444-449.
34. K. Wakabayashi, C-Based High-Level Synthesis System, "CYBER"-Design Experience-, vol. 41, pp. 264-268, July 2000.
35. SYNOPSYS Design Compiler, VSS and Cyclone User Manual, http://www.synopsys.com
36. TSMC 0.25mm Process High-Density Single-Port SRAM (HD-SRAM-SP) Generator User Manual, http://www.artisan.com
37. Cadence Openbook SE 5.3, IC 4.4.5 and LVD 3.0, http://www.cadence.com