On-demand design service innovations

IBM Journal of Research and Development

Volumn 48, Issue 5-6, 2004, Pages 751-765

  Shimizu, Shigenori ^a   Ishikawa, Hiroshi ^a   Satoh, Akashi ^a   Aihara, Toru ^a  

^a IBM RESEARCH TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS; MACROS; REQUIREMENTS ENGINEERING; SECURITY OF DATA; SOFTWARE PROTOTYPING; SYSTEMS ENGINEERING;

ON DEMAND DESIGN SERVICES; SYSTEM EMULATION TOOL;

EMBEDDED SYSTEMS;

EID: 10844293546     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.485.0751     Document Type: Article

References (38)

1. S. Walkers, "Reprogrammable Hardware Emulation Automates System-Level ASIC Validation," Proceedings of the Wescon/'90 Conference Records, Electron Conventions Mgt., November 1990, pp. 140-143.
2. W.-J. Fang and A. C.-H. Wu, "Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication," Proceedings of the 35th Design Automation Conference (DAC), June 1998, pp. 283-286.
3. M. Meerwein, C. Baumgartner, T. Wieja, and W. Glauert, "Embedded Systems Verification with FPGA-Enhanced In-Circuit Emulator," Proceedings of the 13th International Symposium on System Synthesis, September 2000, pp. 143-148.
4. Virtex-II Pro Platform FPGAs: Complete Data Sheet, Xilinx, DS083 March 9, 2004; see http://direct.xilinx.com/bvdocs/publications/ds083.pdf
5. A. Satoh, Y. Kobayashi, H. Niijima, N. Ohba, S. Munetoh, and S. Sone, "A High-Speed Small RSA Encryption LSI with Low Power Dissipation," Proceedings of the 1997 Information Security Workshop (ISW '97), September 1997, pp. 174-187.
6. Sony Electronics Inc.; see http://bssc.sel.sony.com/Professional/puppy/index.html.
7. R. Rivest, A. Shamir, and L. Adleman, "A Method for Obtaining Digital Signatures and Public-Key Cryptosystems," Commun. ACM 21, No. 2, 120-126 (February 1978).
8. National Institute of Standards and Technology, "Data Encryption Standard (DES)," FIPS Publication 46-3, October 1999; see http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf.
9. "IBM PowerPC 405LP," IBM PowerPC processor news (October 2001); see http://www-306.ibm.com/chips/products/powerpc/newsletter/oct2001 /new-prod2.html
10. National Institute of Standards and Technology, "Advanced Encryption Standard (AES)," FIPS Publication 197, November 2001; see http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf.
11. A. Satoh, S. Morioka, S. Munetoh, and K. Takano, "A Compact Rijndael Hardware Architecture with S-Box Optimization," Advances in Cryptology (ASIACRYPT 2001); published in Lecture Notes in Computer Science 2248 (C. Boyd, Ed.), 239-254 (2001).
12. V. S. Miller, "Use of Elliptic Curve in Cryptography," Proceedings of Advances in Cryptology (Crypto '85); published in Lecture Notes in Computer Science 218 (H. C. Williams, Ed. ), 417-426 (1986).
13. N. Koblitz, "Elliptic Curve Cryptosystems," Math. Comp. 48 203-209 (1987).
14. M. Aigner, "Scalable AES HW-Module," Institute for Applied Information Processing and Communications, Graz University of Technology, July 2001; see http://www.iaik.tu-graz.ac.at/research/ vlsi%20design/aes% 20for%20smartcards/aes-brochure/ IAIK_AES_Module.pdf.
15. Helion Technology, Overview Datasheet - High Performance AES (Rijndael) cores for ASIC, 2002; see http://www.heliontech.com/downloads/aes_asic_helioncore.pdf.
16. Ocean Logic Pty Ltd., OLÆS-AES Core family Rev 1.4; see http://www.ocean-logic.com/pub/OLÆS.pdf.
17. Amphion Semiconductor, CS5265/75-AES Simplex Encryption/Decryption Cores; see http://www.amphion.com/e-d.html.
18. S. Mangard, M. Aigner, and S. Dominikus, "A Highly Regular and Scalable AES Hardware Architecture," IEEE Trans. Computers 52, No. 4, 483-491 (April 2003).
19. S. Morioka and A. Satoh, "A 10 Gbps Full-AES Crypto Hardware with a Twisted-BDD S-Box Architecture," Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02), September 2002, pp. 98-103.
20. 2155, IEEE J. Selected Areas in Commun. 11, No. 5, 804-813 (June 1993).
21. S. Sutikno, A. Surya, and R. Effendi, "An Implementation of ElGamal Elliptic Curves Cryptosystems," Proceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'98), November 1998, pp. 483-486.
22. S. Sutikno, R. Effendi, and A. Surya, "Design and Implementation of Arithmetic Processor F2155, for Elliptic Curve Cryptosystems," Proceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'98), November 1998, pp. 647-650.
23. K. H. Leung, K. W. Ma, W. K. Wong, and P. H. W. Leong, "FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor," Proceedings of the 2000 IEEE Symposium on Field Programmable Custom Computing Machines (FCCM), April 2000, pp. 68-76.
24. M. Ernst, S. Klupsch, O. Hauck, and S. A. Huss, "Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems," Proceedings of the 12th International Workshop on Rapid System Prototyping (RSP 2001), June 2001, pp. 24-31.
25. L. Gao, S. Shrivastava, and G. E. Sobelman, "Elliptic Curve Scalar Multiplier Design Using FPGAs," Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems (CHES'99); published in Lecture Notes in Computer Science 1717 (Ç. K. Koç and C. Paar, Eds.), 257-268 (August 1999).
26. M. C. Rosner, "Elliptic Curve Cryptosystems on Reconfigurable Hardware," Master's Thesis, ECE Department, Worcester Polytechnic Institute, Worcester, MA, May 1998.
27. G. Orlando and C. Paar, "A High-Performance Reconfigurable Elliptic Curve Processor for GF(2m)," Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2000); published in Lecture Notes in Computer Science 1965, 41-56 (August 2000).
28. N. P. Smart, "The Hessian Form of an Elliptic Curve," Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2001); published in Lecture Notes in Computer Science 2162 (Ç. K. Koç. D. Naccache, and C. Paar, Eds.), 118-125 (May 2001).
29. m on an FPGA," Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2000); published in Lecture Notes in Computer Science 1965, 25-40 (August 2000).
30. J. Goodman and A. Chandrakasan, "An Energy Efficient Reconfigurable Public-Key Cryptography Processor Architecture," Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2000); published in Lecture Notes in Computer Science 1965, 175-190 (August 2000).
31. G. Orlando and C. Paar, "A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware," Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2001); published in Lecture Notes in Computer Science 2162, 349-363 (May 2001).
32. S.-B. Xu and L. Batina, "Efficient Implementation of Elliptic Curve Cryptosystems on an ARM7 with Hardware Accelerator," Proceedings of the 4th International Information Security Conference (ISC'01); published in Lecture Notes in Computer Science 2200, 266-279 (October 2001).
33. P. L. Montgomery, "Modular Multiplication Without Trial Division," Math. Comp. 44, No. 170, 519-521 (1985).
34. Ç. K. Koç, T. Acar, and B. S. Kaliski, Jr., " Analyzing and Comparing Montgomery Multiplication Algorithms," IEEE Micro 16 No. 3, 26-33 (June 1996).
35. k)," Designs, Codes, & Cryptog. 14, No. 1, 57-69 (April 1998).
36. A. Satoh and K. Takano, "A Scalable Dual-Field Elliptic Curve Cryptographic Processor," IEEE Trans. Computers 52, No. 4, 449-460 (April 2003).
37. National Institute of Standards and Technology, "Digital Signature Standard (DSS)," FIPS PUB 186-2, January 2000; see http://csrc.nist.gov/publications/fips/fips186-2 /fips186-2-change1.pdf
38. J. Postel, "Domain Name System Structure and Delegation," RFC 1591 (RFC1591), March 1994; see www.faqs.org/rfcs/rfc1591.html.