Electrical characterization of 12 nm EJ-MOSFETs on SOI substrates

Solid-State Electronics

Volumn 48, Issue 5, 2004, Pages 739-745

  Henschel, W ^a   Wahlbrink, T ^a   Georgiev, Y M ^a   Lemme, M ^a   Mollenhauer, T ^a   Vratzov, B ^a   Fuchs, A ^a   Kurz, H ^a   Kittler, M ^b   Schwierz, F ^b  

^a AMO GMBH   (Germany)

^b ILMENAU UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

12 nm gate length; EJ MOSFET; Electron beam lithography; HSQ; Shallow junction; SOI

Indexed keywords

CHEMICAL VAPOR DEPOSITION; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRON BEAM LITHOGRAPHY; ETCHING; GATES (TRANSISTOR); POLYSILICON; RAPID THERMAL ANNEALING; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; TRANSMISSION ELECTRON MICROSCOPY;

EJ-MOSFET; HSQ; SOI;

MOSFET DEVICES;

EID: 10744233152     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2003.09.037     Document Type: Article

References (10)

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