Transistor characteristics of 14-nm-gate-length EJ-MOSFET's

IEEE Transactions on Electron Devices

Volumn 47, Issue 4, 2000, Pages 856-860

  Kawaura, Hisao ^a   Sakamoto, Toshitsugu ^a   Baba, Toshio ^a   Ochiai, Yukinori ^a   Fujita, JuN'Ichi ^a   Sone, JuN'ichi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENT MEASUREMENT; GATES (TRANSISTOR); LEAKAGE CURRENTS; QUANTUM THEORY; SEMICONDUCTOR DEVICE MANUFACTURE; THERMOANALYSIS;

SUBTHRESHOLD LEAKAGE CURRENTS;

MOSFET DEVICES;

EID: 0033884610     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.831004     Document Type: Article

References (6)

1. M.OnoetaL, Sub-50 nm gate length n-mosfets with lOnm phosphorus source and drain junctions, in IEDM Tech. Dig., 1993, pp. 119-122.
2. Y. Ochiai, S. Manako, S. Samukawa, K. Takeuchi, and T. Yamamoto, Accurate nano-EB lithography for 40-nm gate MOSFETs, Microelectron. Eng., vol. 30, pp. 415-118, 1996.
3. J. Fujita, Y Ohmishi, Y Ochiai, and S. Matsui, Ultrahigh resolution of calixarene negative resist in electron beam lithography, Appl. Phys. Lett., vol. 68, pp. 1297-1299, 1996.
4. H. Noda, F. Murai, andS. Kimura, Threshold voltage controlled 0.1 μm MOSFET utilizing inversion layer as extremely shallow source/drain, in IEDM Tech. Dig., 1993, pp. 123-126.
5. H. Kawaura et al., Proposal of pseudo source and drain MOSFET's and evaluation for 10-nm gate MOSFETs, in Ext. Abst. Int. Conf. on Solid State Devices and Materials, 1996, pp. 22-24.
6. Transistor oparation of 30-nm gate-length EJ-MOSFETs, IEEE Electron Device Lett., vol. 19, pp. 74-76, Feb. 1998.