Proposal of pseudo source and drain MOSFETs for evaluating 10-nm gate MOSFETs

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 36, Issue 3 SUPPL. B, 1997, Pages 1569-1573

  Kawaura, Hisao ^a   Sakamoto, Toshitsugu ^a   Baba, Toshio ^a   Ochiai, Yukinori ^a   Fujita, Jun'ichi ^a   Matsui, Shinji ^a   Sone, Jun'ichi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

Direct source drain tunneling; Numerical simulation; Pseudo source and drain MOSFET; Short channel effect; Transistor operation; Ultrashallow junction

Indexed keywords

EID: 0001149172     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.36.1569     Document Type: Article

References (10)

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9. 10) However, we have no insurance for validity in a 10-nm regime.
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