Reliability enhancement of analog-to-digital converters (ADCs)

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2001, Pages 347-353

  Singh, Mandeep ^a   Koren, Israel ^a  

^a University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; FAILURE ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; MIXER CIRCUITS; RELIABILITY; SENSITIVITY ANALYSIS;

CRITICAL SYSTEMS; DATA COLLECTION; MIXED SIGNAL CIRCUITS;

ANALOG TO DIGITAL CONVERSION;

EID: 0035194064     PISSN: 10636722     EISSN: None     Source Type: Journal    
DOI: 10.1109/DFTVS.2001.966788     Document Type: Article

References (14)

1. Simulation and analysis of transient faults in digital circuits
2. CMOS circuit design for the prevention of single event upset
3. A statistical load dependency of CPU errors at SLAC
4. IBM experiments in soft fails in computer electronics
5. Transient fault sensitivity analysis of analog-to-digital converters (ADCs)
6. Collection of charge on junction nodes from ion tracks
7. A gate level simulation environment for alpha-particle-induced transient faults
8. All-MOS charge redistribution analog-to-digital conversion techniques-Part I
9. A high speed sample-and-hold technique using a Miller holding capacitor
10. A two-path bandpass sigma-delta modulator with extended noise shaping
11. A 1 mV MOS comparator
12. Fully differential ADC with rail-to-rail common mode range and nonlinear capacitor compensation
13. A logic-level model for α-particle hits in CMOS circuits